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? 2012 microchip technology inc. ds22286a-page 1 mcp3911 features ? two synchronous sampling 16/24-bit resolution delta-sigma a/d converters ? 94.5 db sinad, -106.5 dbc total harmonic distortion (thd) (up to 35th harmonic), 111 db sfdr for each channel ? 2.7v - 3.6v av dd , dv dd ? programmable data rate up to 125 ksps - 4 mhz maximum sampling frequency ? oversampling ratio up to 4096 ? ultra low power shutdown mode with <2 a ? -122 db crosstalk between the two channels ? low drift 1.2v internal voltage reference: 7 ppm/c ? differential voltage reference input pins ? high gain pga on each channel (up to 32v/v) ? phase delay compensation with 1 s time resolution ? separate modulator output pins for each channel ? separate data ready pin for easy synchronization ? individual 24-bit digital offset and gain error correction for each channel ? high-speed 20 mhz spi interface with mode 0,0 and 1,1 compatibility ? continuous read/write modes for minimum communication ? low power consumption (8.9 mw at 3.3v, 5.6 mw at 3.3v in low-power mode, typical) ? available in small 20-lead qfn and ssop pack- ages, pin-to-pin compatible with mcp3901 ? extended temperature range: -40c to +125c applications ? energy metering and power measurement ? automotive ? portable instrumentation ? medical and power monitoring ? audio/voice recognition description the mcp3911 is a 2.7v to 3.6v dual channel analog front end (afe) containing two synchronous sampling delta-sigma analog-to-digital converters (adc), two pgas, phase delay compensation block, low-drift internal voltage reference, modulator output block, digital offset and gain errors calibration registers, and high-speed 20 mhz spi compatible serial interface. the mcp3911 adcs are fully configurable with fea- tures such as: 16/24-bit resolution, osr from 32 to 4096, gain from 1x to 32x, independent shutdown and reset, dithering and auto-zeroing. the communication is largely simplified with the one-byte-long commands including various continuous read/write modes that can be accessed by the direct memory access (dma) of an mcu, and with a separate data ready pin that can be directly connected to an interrupt request (irq) input of an mcu. the mcp3911 is capable of interfacing a large variety of voltage and current sensors including shunts, current transformers, rogowski coils and hall effect sensors. package type osc1/clki 1 2 3 4 20 19 18 17 16 15 14 13 5 6 7 8 osc2 sdi reset dv dd av dd ch0+ ch0- ch1- 12 9 dgnd mdat0 mdat1 dr ch1+ agnd sdo 11 10 refin+/out refin- cs sck sdo 20-lead ssop 20-lead qfn 2 ch1- ch1+ ch0+ sck cs refin+/out osc2 refin- dgnd mdat1 osc1/clki avdd dvdd reset sdi ch0- ep 20 1 19 18 17 3 4 14 13 12 11 6789 21 5 10 15 16 agnd mdat0 dr 3.3v two-channel analog front end
mcp3911 ds22286a-page 2 ? 2012 microchip technology inc. functional block diagram ch0+ ch0- ch1+ ch1- dual ?C adc analog digital sinc 3 + sinc 1 - + pga - + pga ?C modulator amclk dmclk/drclk phase shifter phase <11:0> data_ch0 <23:0> mod<7:0> refin+/out refin- avdd agnd dgnd dvdd mod<3:0> mod<7:4> por avdd monitoring ?C modulator vref+ vref- vrefext voltage reference vref + - por dvdd monitoring sdo sdi sck xtal oscillator mclk osc1 osc2 dr reset digital spi interface clock generation modulator output block mdat1 mdat0 dmclk osr<2:0> pre<1:0> modout<1:0> cs + x + x +
? 2012 microchip technology inc. ds22286a-page 3 mcp3911 1.0 electrical characteristics absolute maximum ratings ? v dd ..................................................................... -0.3v to 4.0v digital inputs and outputs w.r.t. a gnd ................ --0.3v to 4.0v analog input w.r.t. a gnd ..................................... ....-2v to +2v v ref input w.r.t. a gnd ............................... -0.6v to v dd +0.6v storage temperature .....................................-65c to +150c ambient temp. with power applied ................-65c to +125c soldering temperature of leads (10 seconds) ............. +300c esd on the analog inputs (hbm,mm) ................. 4.0 kv, 200v esd on all other pins (hbm,mm) ........................4.0 kv, 200v ? notice : stresses above those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions, above those indi- cated in the operational listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 1.1 electrical specifications table 1-1: analog specifications target table electrical specifications: unless otherwise indicated, all parameters apply at av dd = dv dd = 2.7v to 3.6v, mclk = 4 mhz; pre<1:0> = 00; osr = 256; gain = 1; vr efext=0, clkext=1, az_freq=0, dither<1:0>=11, boost<1:0> = 10; v cm =0v; t a = -40c to +125c; v in = 1.2 v pp = 424 mv rms @ 50/60 hz on both channels. sym characteristic min typ max units test conditions adc performance resolution (no missing codes) 24 -- -- bits osr = 256 or greater f s (dmclk) sampling frequency 1 4 mhz for maximum condi- tion, boost<1:0> = 11 f d (drclk) output data rate 4 125 ksps for maximum condi- tion, boost<1:0> = 11, osr = 32 ch0+/- analog input absolute voltage on ch0+, ch0-, ch1+, ch1- pins -1 +1 v all analog input channels, measured to agnd i in analog input leakage current +/-1 na reset<1:0>=11, mclk running continuously (ch n+ -ch n- ) differential input voltage range -600/gain +600/ gain mv v ref =1.2v, proportional to v ref v os offset error -1 0.2 +1 mv (note 4) offset error drift 0.5 v/c ge gain error -4 +4 % (note 4) note 1: this specification implies that the adc output is valid over this entire differential range and t hat there is no distortion or instability across this input range. dynamic performance specified at -0.5 db below the maximum signal range, v in = 1.2vpp = 424 mv rms , v ref = 1.2v @ 50/60 hz. see terminology section for definition. this parameter is established by characterization and not 100% test ed. see performance graphs for other than default settings provided here. 2: for these operating currents the following configuration bit settings apply: shutdown<1:0>=00, reset<1:0>=00, vrefext=0, clkext=0. 3: for these operating currents the following configuration bit settings apply: shutdown<1:0>=11, vrefext=1, clkext=1. 4: applies to all gains. offset and gain errors depend on pga gain setting, see typical performance curves for typical per- formance. 5: outside of this range, adc accuracy is not specified. an extended input range of +/-2 v can be applied continuously to the part with no damage. 6: for proper operation, and for optimizing adc accuracy, amclk should be limited to the maximum frequency defined in the table 5-2 as a function of the boost and pga setting chosen. mc lk can take larger values as long as the pres- caler settings (pre<1:0>) limit amclk=mclk/prescale in the defined range in the table 5-2 .
mcp3911 ds22286a-page 4 ? 2012 microchip technology inc. gain error drift 1 ppm/c inl integral non-linearity 5 ppm z in differential input impedance 232 ? ? k g=1, proportional to 1/ amclk 142 ? ? k g=2, proportional to 1/ amclk 72 ? ? k g=4, proportional to 1/ amclk 38 ? ? k g=8, proportional to 1/ amclk 36 ? ? k g=16, proportional to 1/ amclk 33 ? ? k g=32, proportional to 1/ amclk sinad signal-to-noise and distortion ratio (note 1) 92 94.5 ? db thd total harmonic distortion (note 1) -106.5 -103 dbc includes the first 35 har- monics snr signal to noise ratio (note 1) 92 95 db sfdr spurious free dynamic range (note 1) 111 dbfs ctalk crosstalk (50, 60 hz) ? -122 ? db ac psrr ac power supply rejection ? -73 ? db av dd = dv dd = 3.3v + 0.6vpp, 50/60 hz, 100/120 hz dc psrr dc power supply rejection ? -73 ? db av dd = dv dd = 2.7v to 3.6v dc cmrr dc common mode rejection ? -105 ? db v cm from -1v to +1v internal voltage reference v ref tolerance 1.176 1.2 1.224 v vrefext = 0, t a = 25c only tcv ref temperature coefficient ? 7 ? ppm/c t a = -40c to +125c, vrefext = 0 table 1-1: analog specifications target table (continued) electrical specifications: unless otherwise indicated, all parameters apply at av dd = dv dd = 2.7v to 3.6v, mclk = 4 mhz; pre<1:0> = 00; osr = 256; gain = 1; vr efext=0, clkext=1, az_freq=0, dither<1:0>=11, boost<1:0> = 10; v cm =0v; t a = -40c to +125c; v in = 1.2 v pp = 424 mv rms @ 50/60 hz on both channels. sym characteristic min typ max units test conditions note 1: this specification implies that the adc output is valid over this entire differential range and that there is no distortion or instability across this input range. dynamic performance specified at -0.5 db below the maximum signal range, v in = 1.2vpp = 424 mv rms , v ref = 1.2v @ 50/60 hz. see terminology section for definition. this parameter is established by characterization and not 100% tested. see performanc e graphs for other than default settings provided here. 2: for these operating currents the following configuration bit settings apply: shutdown<1:0>=00, reset<1:0>=00, vrefext=0, clkext=0. 3: for these operating currents the following configuration bit settings apply: shutdown<1:0>=11, vrefext=1, clkext=1. 4: applies to all gains. offset and gain errors depend on pga gain setting, see typical performance curves for typical per- formance. 5: outside of this range, adc accuracy is not specified. an extended input range of +/-2 v can be applied continuously to the part with no damage. 6: for proper operation, and for optimizing adc accuracy, amclk should be limited to the maximum frequency defined in the table 5-2 as a function of the boost and pga setting chosen. mc lk can take larger values as long as the pres- caler settings (pre<1:0>) limit amclk=mclk/prescale in the defined range in the table 5-2 .
? 2012 microchip technology inc. ds22286a-page 5 mcp3911 zoutv ref output impedance 2 ? k vrefext = 0 ai dd v ref internal voltage reference operating current 25 ? a vrefext=0, shut- down<1:0>=11 voltage reference input input capacitance ? ? 10 pf v ref differential input voltage range (vref+ - vref -) 1.1 ? 1.3 v vrefext = 1 v ref+ absolute voltage on refin+ pin v ref- + 1.1 ?v ref- + 1.3 v vrefext = 1 v ref- absolute voltage refin- pin -0.1 ? +0.1 v refin- should be con- nected to agnd when vrefext=0 master clock input f mclk master clock input frequency range ? 20 mhz clkext = 1, (note 6) f xtal crystal oscillator operating frequency range 1 ? 20 mhz clkext = 0, (note 6) amclk analog master clock ? ? 16 mhz (note 6) power supply av dd operating voltage, analog 2.7 ? 3.6 v dv dd operating voltage, digital 2.7 ? 3.6 v i dd,a operating current, analog (note 2) ? 1.5 2.3 ma boost<1:0>=00 ? 1.8 2.8 ma boost<1:0>=01 ? 2.5 3.5 ma boost<1:0>=10 ? 4.4 6.25 ma boost<1:0>= 11 i dd,d operating current, digital ? 0.2 0.3 ma mclk = 4 mhz, proportional to mclk ? 0.7 ? ma mclk = 16 mhz, pro- portional to mclk i dds,a shutdown current, analog ? ? 1 a av dd pin only (note 3) i dds,d shutdown current, digital ? ? 1 a dv dd pin only ( note 3) table 1-1: analog specifications target table (continued) electrical specifications: unless otherwise indicated, all parameters apply at av dd = dv dd = 2.7v to 3.6v, mclk = 4 mhz; pre<1:0> = 00; osr = 256; gain = 1; vr efext=0, clkext=1, az_freq=0, dither<1:0>=11, boost<1:0> = 10; v cm =0v; t a = -40c to +125c; v in = 1.2 v pp = 424 mv rms @ 50/60 hz on both channels. sym characteristic min typ max units test conditions note 1: this specification implies that the adc output is valid over this entire differential range and t hat there is no distortion or instability across this input range. dynamic performance specified at -0.5 db below the maximum signal range, v in = 1.2vpp = 424 mv rms , v ref = 1.2v @ 50/60 hz. see terminology section for definition. this parameter is established by characterization and not 100% test ed. see performance graphs for other than default settings provided here. 2: for these operating currents the following configuration bit settings apply: shutdown<1:0>=00, reset<1:0>=00, vrefext=0, clkext=0. 3: for these operating currents the following configuration bit settings apply: shutdown<1:0>=11, vrefext=1, clkext=1. 4: applies to all gains. offset and gain errors depend on pga gain setting, see typical performance curves for typical per- formance. 5: outside of this range, adc accuracy is not specified. an extended input range of +/-2 v can be applied continuously to the part with no damage. 6: for proper operation, and for optimizing adc accuracy, amclk should be limited to the maximum frequency defined in the table 5-2 as a function of the boost and pga setting chosen. mc lk can take larger values as long as the pres- caler settings (pre<1:0>) limit amclk=mclk/prescale in the defined range in the table 5-2 .
mcp3911 ds22286a-page 6 ? 2012 microchip technology inc. 1.2 serial interface characteristics table 1-2: serial dc characteristics table electrical specifications: unless otherwise indicated, all parameters apply at dv dd = 2.7 to 3.6v, t a = -40c to +125c, c load = 30pf, applies to all digital i/o. sym characteristics min typ max units test conditions v ih high-level input voltage 0.7 dv dd ? v schmitt triggered v il low-level input voltage ? 0.3 dv dd v schmitt triggered i li input leakage current ? ? 1 a cs = dv dd , v in = dgnd to dv dd i lo output leakage current ? ? 1 a cs = dv dd , v out = dgnd or dv dd v hys hysteresis of schmitt trig- ger inputs ?200 mv (note 2) , dv dd = 3.3v only v ol low-level output voltage ??0.4vi ol = +2.1ma, dv dd = 3.3v v oh high-level output voltage dv dd -0.5 ? ? v i oh = -2.1ma, dv dd = 3.3v c int internal capacitance (all inputs and outputs) ??7 pft a = 25c, sck = 1.0 mhz, dv dd =3.3v (note 1) note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is established by char acterization and not production tested. table 1-3: serial ac characteristics table electrical specifications: unless otherwise indicated, all parameters apply at dv dd = 2.7 to 3.6v, t a = -40c to +125c, gain = 1, c load = 30pf. sym characteristics min typ max units test conditions f sck serial clock frequency ? ? 20 mhz t css cs setup time 25 ? ? ns t csh cs hold time 50 ? ? ns t csd cs disable time 50 ? ? ns t su data setup time 5 ? ? ns t hd data hold time 10 ? ? ns t hi serial clock high time 20 ? ? ns t lo serial clock low time 20 ? ? ns t cld serial clock delay time 50 ? ? ns t cle serial clock enable time 50 ? ? ns t do output valid from sck low ? ? 25 ns t domdat modulator output valid from amclk high ??1/(2*amclk) s t ho output hold time 0 ? ? ns (note 1) t dis output disable time ? ? 25 ns (note 1) t mclr reset pulse width (reset )100 ? ? ns t dodr data transfer time to dr (data ready ) ?25 ns (note 2) note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is established by char acterization and not production tested.
? 2012 microchip technology inc. ds22286a-page 7 mcp3911 figure 1-1: serial output timing diagram. t modsu modulator mode entry to modulator data present ?100 ns t drp data ready pulse low time 1/dmclk ?s table 1-3: serial ac characteristics table (continued) electrical specifications: unless otherwise indicated, all parameters apply at dv dd = 2.7 to 3.6v, t a = -40c to +125c, gain = 1, c load = 30pf. sym characteristics min typ max units test conditions note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is established by char acterization and not production tested. table 1-4: temperature specifications table electrical specifications: unless otherwise indicated, all parameters apply at av dd = 2.7 to 3.6v, dv dd = 2.7 to 3.6v. parameters sym min typ max units conditions temperature ranges operating temperature range t a -40 ? +125 c (note 1) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 20l ssop ja ? 89.3 ? c/w thermal resistance, 20l qfn ja ?43 ? c/w note 1: the internal junction temperature (t j ) must not exceed the absolute maximum specification of +150c. t csh t dis t hi t lo f sck cs sck sdo msb out lsb out sdi mode 1,1 mode 0,0 t ho t do don?t care
mcp3911 ds22286a-page 8 ? 2012 microchip technology inc. figure 1-2: serial input timing diagram. figure 1-3: data ready pulse / sampling timing diagram. cs sck sdi lsb in msb in mode 1,1 mode 0,0 t css t su t hd t csd t csh t cld t cle sdo hi-z t hi t lo f sck dr sck t drp sdo 1 / f d t dodr
? 2012 microchip technology inc. ds22286a-page 9 mcp3911 h figure 1-4: timing diagrams, continued. cs v ih waveform for t dis hi-z 90% 10% t dis sdo sck sdo t do timing waveform for t do mdat osc1/clki timing waveform for mdat0/1 modulator output function t domdat
mcp3911 ds22286a-page 10 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds22286a-page 11 mcp3911 2.0 typical performance curves note: unless otherwise indicated, av dd = 3.3v, dv dd = 3.3v; t a = 25c, mclk = 4 mhz; prescale = 1; osr = 256; gain = 1; dithering = maximum; v in = -0.5 dbfs @ 60 hz, vrefext = 0; clkext = 1, az_freq = 0; boost = 1x. figure 2-1: spectral response. figure 2-2: spectral response. figure 2-3: thd histogram. figure 2-4: spectral response. figure 2-5: spectral response. figure 2-6: sinad histogram. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. e ncy of occurrence -107.3 -107.1 -107.0 -106.8 -106.7 -106.5 -106.4 -106.2 -106.1 -105.9 -105.8 frequ e total harmonic distortion (-dbc) n cy of occurrence 94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 freque n signal-to-noise and distortion ratio (db)
mcp3911 ds22286a-page 12 ? 2012 microchip technology inc. note: unless otherwise indicated, av dd = 3.3v, dv dd = 3.3v; t a = 25c, mclk = 4 mhz; prescale = 1; osr = 256; gain = 1; dithering = maximum; v in = -0.5 dbfs @ 60 hz, vrefext = 0; clkext = 1, az_freq = 0; boost = 1x. figure 2-7: spurious free dynamic range histogram. figure 2-8: snr histogram. figure 2-9: noise histogram. figure 2-10: enob sinad histogram. figure 2-11: enob snr histogram. figure 2-12: thd vs. osr. e ncy of occurrence 104.5 106 107.5 109 110.5 112 113.5 115 frequ e spurious free dynamic range (dbfs) u ency of occurrence 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 95.6 95.8 95.9 frequ signal to noise ratio (db) 1000 1500 2000 2500 3000 3500 4000 4500 5000 u ency of occurrence channel 1 v in = 0v t a = 25 c 16384 consecutive readings 0 500 1000 freq u output code (lsb) q uencyofoccurrence 15.3 15.4 15.4 15.4 15.5 15.5 15.5 15.5 15.6 15.6 fre q effectivenumberofbits(sinad) q uencyofoccurrence 15.4 15.4 15.5 15.5 15.5 15.5 15.6 15.6 15.6 15.6 fre q effectivenumberofbits(snr) - 80 -70 -60 -50 -40 -30 -20 -10 0 m onic distortion (dbc) di t h e rin g = m ed i u m dithering = minimum dithering = none -120 -110 -100 -90 80 32 64 128 256 512 1024 2048 4096 total har m oversampling ratio (osr) dithering = maximum te g ed u
? 2012 microchip technology inc. ds22286a-page 13 mcp3911 note: unless otherwise indicated, avdd = 3.3v, dvdd = 3.3v; ta = 25 c, mclk = 4 mhz; prescale = 1; osr = 256; gain = 1; dithering = maximum; vin = -0.5 dbfs @ 60 hz, vrefext = 0; clkext = 1, az_freq = 0; boost = 1x. figure 2-13: sinad vs. osr. l figure 2-14: snr vs.osr. figure 2-15: sfdr vs. osr. figure 2-16: thd vs. mclk. figure 2-17: sinad vs. mclk. figure 2-18: snr vs. mclk. 40 50 60 70 80 90 100 110 120 o -noise and distortion ratio (db) dithering = maximum dithering = medium dithering = minimum dithering = none 0 10 20 30 40 32 64 128 256 512 1024 2048 4096 signal-t o oversampling ratio (osr) 40 50 60 70 80 90 100 110 120 - to-noise ratio (db) dithering = maximum dithering = medium dithering = minimum dithering = none 0 10 20 30 40 32 64 128 256 512 1024 2048 4096 signal - oversampling ratio (osr) 50 60 70 80 90 100 110 120 130 140 r ee dynamic range (dbfs) dithering = maximum dithering = medium dithering = minimum dithering = none 0 10 20 30 40 32 64 128 256 512 1024 2048 4096 spurious f r oversampling ratio (osr) - 90 -80 -70 -60 -50 -40 -30 -20 -10 0 rmonic distortion (dbc) boost = 0.5x boost = 0.66x boost = 1x -120 -110 -100 90 0 5 10 15 20 25 30 total ha mclk frequency (mhz) boost = 2x 40 50 60 70 80 90 100 110 120 - noise and distortion ratio (db) boost =05x boost = 0.66x boost = 2x boost = 1x 0 10 20 30 40 0 5 10 15 20 25 30 signal-to - mclk frequency (mhz) boost =0 . 5x 40 50 60 70 80 90 100 110 120 al to noise ratio (db) boost = 0.5x boost = 0.66x boost = 2x boost = 1x 0 10 20 30 0 5 10 15 20 25 30 sign mclk frequency (mhz)
mcp3911 ds22286a-page 14 ? 2012 microchip technology inc. note: unless otherwise indicated, av dd = 3.3v, dv dd = 3.3 v; t a = 25c, mclk = 4 mhz; prescale = 1; osr = 256; gain = 1; dithering = maximum; v in = -0.5 dbfs @ 60 hz, vrefext = 0; clkext = 1, az_freq = 0; boost = 1x. figure 2-19: sfdr vs. mclk. figure 2-20: sinad vs. gain. figure 2-21: sinad vs. gain (dithering off). figure 2-22: sinad vs. gain vs. az speed chart. figure 2-23: thd vs. input signal amplitude. figure 2-24: sinad vs. input signal amplitude. 40 50 60 70 80 90 100 110 120 free dynamic range (dbfs) boost = 0.5x boost = 0.66x boost = 2x boost = 1x 0 10 20 30 0 5 10 15 20 25 30 spurious frequency (mhz) 40 50 60 70 80 90 100 110 120 n oise and distortion r atio (db) osr = 32 osr = 64 osr = 128 osr = 256 osr = 4096 osr = 2048 osr = 1024 osr = 512 0 10 20 30 12481632 signal to n r gain (v/v) 70 75 80 85 90 95 100 12481632 signal to noise and distortion ratio (db) gain (v/v) auto zero speed = fast auto zero speed = slow 80 -70 -60 -50 -40 -30 -20 -10 0 o nic distortion (dbc) -120 -110 -100 -90 - 80 -6 -5 -4 -3 -2 -1 0 1 2 3 total harm o input signal amplitude (dbfs) channel 0 channel 1 0 10 20 30 40 50 60 70 80 90 100 110 120 -6 -5 -4 -3 -2 -1 0 1 2 3 signal to noise and distortion ratio (db) input signal amplitude (dbfs) channel 0 channel 1
? 2012 microchip technology inc. ds22286a-page 15 mcp3911 note: unless otherwise indicated, av dd = 3.3v, dv dd = 3.3v; t a = 25c, mclk = 4 mhz; prescale = 1; osr = 256; gain = 1; dithering = maximum; v in = -0.5 dbfs @ 60 hz, vrefext = 0; clkext = 1, az_freq = 0; boost = 1x. figure 2-25: snr vs. input signal amplitude. figure 2-26: sfdr vs. input signal amplitude. figure 2-27: thd vs. temperature. figure 2-28: sinad vs. temperature. figure 2-29: snr vs. temperature. figure 2-30: sfdr vs. temperature. 30 40 50 60 70 80 90 100 110 120 to noise ratio (db) channel 0 channel 1 0 10 20 30 -6 -5 -4 -3 -2 -1 0 1 2 3 signal input signal amplitude (dbfs) 30 40 50 60 70 80 90 100 110 120 s free dyanmic raneg (dbfs) channel 0 channel 1 0 10 20 30 -6 -5 -4 -3 -2 -1 0 1 2 3 spuriou s input signal amplitude (dbfs) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -50 -25 0 25 50 75 100 125 150 total harominc distortion (dbc) temperature (c) g=32 g=16 g=8 g=4 g=2 g=1 0 10 20 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 150 signal to noise and distortion ration (db) temperature (c) g=32 g=16 g=8 g=4 g=2 g=1 0 10 20 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 150 signal to noise ratio (db) temperature (c) g=32 g=16 g=8 g=4 g=2 g=1 0 10 20 30 40 50 60 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 150 spurious free dynamic range (dbfs) temperature (c) g=32 g=16 g=8 g=4 g=2 g=1
mcp3911 ds22286a-page 16 ? 2012 microchip technology inc. note: unless otherwise indicated, av dd = 3.3v, dv dd = 3.3v; t a = 25c, mclk = 4 mhz; prescale = 1; osr = 256; gain = 1; dithering = maximum; v in = -0.5 dbfs @ 60 hz, vrefext = 0; clkext = 1, az_freq = 0; boost = 1x. figure 2-31: channel 0 offset vs. temperature. figure 2-32: channel 1 offset vs. temperature. figure 2-33: channel to channel offset match vs. temperature. figure 2-34: gain error vs. temperature. figure 2-35: internal voltage reference vs. temperature. figure 2-36: internal voltage reference vs. supply voltage. 50 100 150 200 250 300 350 400 a nnel 0 offset ( v) g=32 g=16 g=8 g=4 -100 -50 0 50 -50 -25 0 25 50 75 100 125 150 ch a temperature (c) g=2 g=1 50 100 150 200 250 300 350 400 a nnel 1 offset ( v) g=32 g=16 g=8 g=4 -100 -50 0 50 -50 -25 0 25 50 75 100 125 150 ch a temperature (c) g=2 g=1 -80 -60 -40 -20 0 o ffset error ( v) channel 0 channel 1 -120 -100 -50 -25 0 25 50 75 100 125 150 o temperature (c) channel 0 1.1997 1.1998 1.1999 1.2000 1.2001 1.2002 1.2003 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 internal voltage reference (v) v dd (v)
? 2012 microchip technology inc. ds22286a-page 17 mcp3911 note: unless otherwise indicated, av dd = 3.3v, dv dd = 3.3v; t a = 25c, mclk = 4 mhz; prescale = 1; osr = 256; gain = 1; dithering = maximum; v in = -0.5 dbfs @ 60 hz, vrefext = 0; clkext = 1, az_freq = 0; boost = 1x. figure 2-37: v ref drift data histogram chart. figure 2-38: integral non-linearity (dithering maximum). figure 2-39: integral non-linearity (dithering off). figure 2-40: operating current vs. mclk, v dd = 3.3v. figure 2-41: operating current vs. mclk, v dd = 2.7v. 03691215182124 frequency of occurrence internal voltage reference drift (ppm/c) 10 -5 0 5 10 15 20 25 n linearity error (ppm) channel 1 -25 -20 -15 - 10 -0.6 -0.3 0 0.3 0.6 integral no input voltage (v) channel 0 10 -5 0 5 10 15 20 25 n linearity error (ppm) channel 0 channel 1 -25 -20 -15 - 10 -0.6 -0.3 0 0.3 0.6 integral no input voltage (v) channel 1 1. 5 2 2.5 3 3.5 4 4.5 i dd (ma) ai dd , boost = 2x ai dd , boost = 1x ai dd , boost = 0.6x 0 0.5 1 5 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 mclk frequency (mhz) ai dd , boost = 0.5x di dd , all boost settings 1.5 2 2.5 3 3.5 4 i dd (ma) ai dd , boost = 2x ai dd , boost = 1x ai dd , boost = 0.6x 0 0.5 1 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 mclk frequency (mhz) ai dd , boost = 0.5x di dd , all boost settings
mcp3911 ds22286a-page 18 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds22286a-page 19 mcp3911 3.0 pin description the descriptions of the pins are listed in tab l e 3 - 1 . table 3-1: pin function table 3.1 master reset (r eset ) this pin is active low and places the entire chip in a reset state when active. when reset =0, all registers are reset to their default value, no communication can take place, and no clock is distributed inside the part, except in the input struc- ture if mclk is applied (if idle, then no clock is distrib- uted). this state is equivalent to a por state. since the default state of the adcs is on, the analog power consumption, when reset =0, is equivalent to when reset =1. only the digital power consumption is largely reduced because this current consumption is essentially dynamic and is reduced drastically when there is no clock running. all the analog biases are enabled during a reset so that the part is fully operational just after a reset rising edge, if the mclk is applied during the rising edge. if not applied, there is a small time after reset where the conversion may not be accurate corresponding to the startup of the charge pump of the input structure. this input is schmitt triggered. 3.2 digital v dd (dv dd ) dv dd is the power supply pin for the digital circuitry within the mcp3911. this pin requires appropriate bypass capacitors and should be maintained between 2.7v and 3.6v for specified operation. 3.3 analog v dd (av dd ) av dd is the power supply pin for the analog circuitry within the mcp3911. this pin requires appropriate bypass capacitors and should be maintained to 2.7v and 3.6v for specified operation. 3.4 adc differential analog inputs (chn+/chn-) ch0- and ch0+, and ch1- and ch1+, are the two fully-differential analog voltage inputs for the delta-sigma adcs. pin no. ssop pin no. qfn symbol function 1 18 reset master reset logic input pin 219 dv dd digital power supply pin 320 av dd analog power supply pin 4 1 ch0+ non-inverting analog input pin for channel 0 5 2 ch0- inverting analog input pin for channel 0 6 3 ch1- inverting analog input pin for channel 1 7 4 ch1+ non-inverting analog input pin for channel 1 8 5 agnd analog ground pin, return path for internal analog circuitry 9 6 refin+/out non-inverting voltage reference input and internal reference output pin 10 7 refin- inverting voltage reference input pin 11 8 dgnd digital ground pin, return path for internal digital circuitry 12 9 mdat1 modulator data output pin for channel 1 13 10 mdat0 modulator data output pin for channel 0 14 11 dr data ready signal output pin 15 12 osc1/clki oscillator crystal connection pin or external clock input pin 16 13 osc2 oscillator crystal connection pin 17 14 cs serial interface chip select pin 18 15 sck serial interface clock input pin 19 16 sdo serial interface data input pin 20 17 sdi serial interface data input pin - 21 ep exposed thermal pad. must be connected to agnd.
mcp3911 ds22286a-page 20 ? 2012 microchip technology inc. the linear and specified region of the channels are dependent on the pga gain. this region corresponds to a differential voltage range of 600 mv/gain with v ref =1.2v. the maximum differential voltage is proportional to the v ref voltage. the maximum absolute voltage, with respect to agnd, for each chn+/- input pin is +/-1v with no distortion and 2v with no breaking after con- tinuous voltage. this maximum absolute voltage is not proportional to the v ref voltage. 3.5 analog ground (agnd) agnd is the ground connection to internal analog circuitry (see the ?functional block diagram? ). to ensure accuracy and noise cancellation, this pin must be connected to the same ground as dgnd, preferably with a star connection. if an analog ground plane is available, it is recommended that this pin be tied to this plane of the pcb. this plane should also reference all other analog circuitry in the system. 3.6 non-inverting reference input, internal reference output (refin+/out) this pin is the non-inverting side of the differential voltage reference input for both adcs or the internal voltage reference output. when vrefext=1, an external voltage reference source can be used, the internal voltage reference is disabled. when using an external differential voltage reference, it should be connected to its v ref+ pin. when using an external single-ended reference, it should be connected to this pin. when vrefext=0, the internal voltage reference is enabled and connected to this pin through a switch. this voltage reference has minimal drive capability and thus needs proper buffering and bypass capacitances (a 0.1 f ceramic capacitor is sufficient in most cases) if used as a voltage source. if the voltage reference is only used as an internal v ref , adding bypass capacitance on refin+/out is not necessary for keeping adc accuracy, but a minimal 0.1 f ceramic capacitance can be connected to avoid emi/emc susceptibility issues due to the antenna cre- ated by the refin+/out pin if left floating. 3.7 inverting reference input (refin-) this pin is the inverting side of the differential voltage reference input for both adcs. when using an external differential voltage reference, it should be connected to its v ref- pin. when using an external single-ended voltage reference, or when vrefext=0 (default) and using the internal voltage reference, this pin should be directly connected to agnd. 3.8 digital ground connection (dgnd) dgnd is the ground connection to internal digital circuitry (see the mcp3911 block diagram). to ensure optimal accuracy and noise cancellation, dgnd must be connected to the same ground as agnd, preferably with a star connection. if a digital ground plane is available, it is recommended that this pin be tied to this plane of the printed circuit board (pcb). this plane should also reference all other digital circuitry in the system. 3.9 modulator data output pin for channel 1 and channel 0 (mdat1/ mdat0) mdat0 and mdat1 are the output pins for the modulator serial bitstreams of adc channels 0 and 1, respectively. these pins are high impedance when their corresponding modout bit is logic low. when the modout<1:0> are enabled, the modulator bitstream of the corresponding channel is present on the pin and updated at the amclk frequency. (see section 5.4 ?modulator output block? for a complete description of the modulator outputs). these pins can be directly connected to a mcu or dsp when a specific digital filtering is needed. 3.10 data ready output (dr ) the data ready pin indicates if a new conversion result is ready to be read. the default state of this pin is high when dr_hiz =1 and is high impedance when dr_hiz =0 (default). after each conversion is finished, a logic low pulse will take place on the data ready pin to indicate the conversion result is ready as an inter- rupt. this pulse is synchronous with the master clock and has a defined and constant width. the data ready pin is independent of the spi interface and acts like an interrupt output. the data ready pin state is not latched and the pulse width (and period) are both determined by the mclk frequency, over-sampling rate, and internal clock pre-scale settings. the dr pulse width is equal to one dmclk period and the frequency of the pulses is equal to drclk (see figure 1-3 ). note: this pin should not be left floating when dr_hiz bit is low; a 100 k pull-up resistor connected to dv dd is recommended.
? 2012 microchip technology inc. ds22286a-page 21 mcp3911 3.11 oscillator and master clock input pins (osc1/clki, osc2) osc1/clki and osc2 provide the master clock (mclk) for the device. when clkext=0, a resonant crystal or clock source with a similar sinusoidal wave- form must be placed across these pins to ensure proper operation. the typical clock frequency specified is 4 mhz. for proper operation, and for optimizing adc accuracy, amclk should be limited to the maximum frequency defined in the ta b l e 5 - 3 in function of the boost and pga setting chosen. mclk can take larger values as long as the prescaler settings (pre<1:0>) limit amclk=mclk/prescale in the defined range in the table 5-3 . appropriate load capacitance should be connected to these pins for proper operation. 3.12 chip select (cs ) this pin is the spi chip select that enables the serial communication. when this pin is high, no communication can take place. a chip select falling edge initiates the serial communication and a chip select rising edge terminates the communication. no communication can take place even when cs is low when reset is low. this input is schmitt-triggered. 3.13 serial data clock (sck) this is the serial clock pin for spi communication. data is clocked into the device on the rising edge of sck. data is clocked out of the device on the falling edge of sck. the mcp3911 interface is compatible with both spi 0,0 and 1,1 modes. spi modes can be changed during a cs high time. the maximum clock speed specified is 20 mhz. this input is schmitt triggered. 3.14 serial data output (sdo) this is the spi data output pin. data is clocked out of the device on the falling edge of sck. this pin stays high impedance during the first command byte. it also stays high impedance during the whole communication for write commands and when cs pin is high or when reset pin is low. this pin is active only when a read command is processed. each read is processed by packet of 8 bits. 3.15 serial data input (sdi) this is the spi data input pin. data is clocked into the device on the rising edge of sck. when cs is low, this pin is used to communicate with a series of 8-bit commands. the interface is half-duplex (inputs and outputs do not happen at the same time). each communication starts with a chip select falling edge followed by an 8-bit command word entered through the sdi pin. each command is either a read or a write command. toggling sdi during a read command has no effect. this input is schmitt triggered.
mcp3911 ds22286a-page 22 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds22286a-page 23 mcp3911 4.0 terminology and formulas this section defines the terms and formulas used throughout this data sheet. the following terms are defined: mclk - master clock amclk - analog master clock dmclk - digital master clock drclk - data rate clock osr - oversampling ratio offset error gain error integral non-linearity error signal-to-noise ratio (snr) signal-to-noise ratio and distortion (sinad) total harmonic distortion (thd) spurious-free dynamic range (sfdr) mcp3911 delta-sigma architecture idle tones dithering crosstalk psrr cmrr adc reset mode hard reset mode (reset = 0) adc shutdown mode full shutdown mode 4.1 mclk - master clock this is the fastest clock present in the device. this is the frequency of the crystal placed at the osc1/osc2 inputs when clkext=0 or the frequency of the clock input at the osc1/clki when clkext=1. see figure 4-1 . 4.2 amclk - analog master clock this is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the config pre<1:0> register bits. the analog portion includes the pgas and the two delta-sigma modulators. figure 4-1: clock sub-circuitry. 4.3 dmclk - digital master clock this is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. this is also the sampling frequency, that is the rate at which the modulator outputs are refreshed. each period of this clock corresponds to one sample and one modulator output. see figure 4-1 . equation 4-1: 4.4 drclk - data rate clock this is the output data rate, i.e., the rate at which the adcs output new data. each new data is signaled by a data ready pulse on the dr pin. this data rate is depending on the osr and the prescaler with the following formula: equation 4-2: table 4-1: mcp3911 oversampling ratio settings config analog master clock prescale pre<1:0> 0 0 amclk = mclk/ 1 (default) 01 amclk = mclk/ 2 10 amclk = mclk/ 4 11 amclk = mclk/ 8 amclk mclk prescale ------------------------------ - = dmclk amclk 4 -------------------- - mclk 4 prescale --------------------------------------- - == drclk dmclk osr ---------------------- amclk 4osr --------------------- mclk 4 osr prescale ---------------------------------------------------------- - ===
mcp3911 ds22286a-page 24 ? 2012 microchip technology inc. since this is the output data rate, and since the decimation filter is a sinc (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. the following table describes the various combinations of osr and prescale and their associated amclk, dmclk and drclk rates. table 4-2: device data rates in function of mclk, osr, and prescale, mclk=4mhz pre <1:0> osr <2:0> osr amclk dmclk drclk drclk (ksps) sinad (db) note 1 enob from sinad (bits) note 1 1 1 1 1 1 4096 mclk/8 mclk/32 mclk/131072 0.035 98 16 1 1 1 1 1 2048 mclk/8 mclk/32 mclk/65536 0.061 98 16 1 1 1 1 1 1024 mclk/8 mclk/32 mclk/32768 0.122 97 15.8 1 1 1 1 1 512 mclk/8 mclk/32 mclk/16384 0.244 96 15.6 1 1 0 1 1 256 mclk/8 mclk/32 mclk/8192 0.488 95 15.5 1 1 0 1 0 128 mclk/8 mclk/32 mclk/4096 0.976 90 14.7 1 1 0 0 1 64 mclk/8 mclk/32 mclk/2048 1.95 83 13.5 1 1 0 0 0 32 mclk/8 mclk/32 mclk/1024 3.9 70 11.3 1 0 1 1 1 4096 mclk/4 mclk/16 mclk/65536 0.061 98 16 1 0 1 1 1 2048 mclk/4 mclk/16 mclk/32768 0.122 98 16 1 0 1 1 1 1024 mclk/4 mclk/16 mclk/16384 0.244 97 15.8 1 0 1 1 1 512 mclk/4 mclk/16 mclk/8192 0.488 96 15.6 1 0 0 1 1 256 mclk/4 mclk/16 mclk/4096 0.976 95 15.5 1 0 0 1 0 128 mclk/4 mclk/16 mclk/2048 1.95 90 14.7 1 0 0 0 1 64 mclk/4 mclk/16 mclk/1024 3.9 83 13.5 1 0 0 0 0 32 mclk/4 mclk/16 mclk/512 7.8125 70 11.3 0 1 1 1 1 4096 mclk/2 mclk/8 mclk/32768 0.122 98 16 0 1 1 1 1 2048 mclk/2 mclk/8 mclk/16384 0.244 98 16 0 1 1 1 1 1024 mclk/2 mclk/8 mclk/8192 0.488 97 15.8 0 1 1 1 1 512 mclk/2 mclk/8 mclk/4096 0.976 96 15.6 0 1 0 1 1 256 mclk/2 mclk/8 mclk/2048 1.95 95 15.5 0 1 0 1 0 128 mclk/2 mclk/8 mclk/1024 3.9 90 14.7 0 1 0 0 1 64 mclk/2 mclk/8 mclk/512 7.8125 83 13.5 0 1 0 0 0 32 mclk/2 mclk/8 mclk/256 15.625 70 11.3 0 0 1 1 1 4096 mclk mclk/4 mclk/16384 0.244 98 16 0 0 1 1 0 2048 mclk mclk/4 mclk/8192 0.488 98 16 0 0 1 0 1 1024 mclk mclk/4 mclk/4096 0.976 97 15.8 0 0 1 0 0 512 mclk mclk/4 mclk/2048 1.95 96 15.6 0 0 0 1 1 256 mclk mclk/4 mclk/1024 3.9 95 15.5 0 0 0 1 0 128 mclk mclk/4 mclk/512 7.8125 90 14.7 0 0 0 0 1 64 mclk mclk/4 mclk/256 15.625 83 13.5 0 0 0 0 0 32 mclk mclk/4 mclk/128 31.25 70 11.3 note 1: for osr = 32 and 64, dither = none. for osr = 128 and higher, dither = maximum. the sinad values are given from gain = 1.
? 2012 microchip technology inc. ds22286a-page 25 mcp3911 4.5 osr - oversampling ratio this is the ratio of the sampling frequency to the output data rate. osr= dmclk/drclk. the default osr is 256, or with mclk = 4 mhz, prescale = 1, amclk = 4 mhz, f s = 1 mhz, f d = 3.90625 ksps. the following bits in the config register are used to change the oversampling ratio (osr). 4.6 offset error this is the error induced by the adc when the inputs are shorted together (v in = 0v). the specification incorporates both pga and adc offset contributions. this error varies with pga and osr settings. the offset is different on each channel and varies from chip to chip. the offset is specified in v. the offset error can be digitally compensated independently on each channel through the offcal registers with a 24-bit calibration word. the offset on the mcp3911 has a low temperature coefficient, see typical performance curves for more information, figure 2-33 . 4.7 gain error this is the error induced by the adc on the slope of the transfer function. it is the deviation expressed in % compared to the ideal transfer function defined by equation 5-3 . the specification incorporates both pga and adc gain error contributions, but not the v ref contribution (it is measured with an external v ref ). this error varies with pga and osr settings. the gain error can be digitally compensated independently on each channel through the gaincal registers with a 24-bit calibration word. the gain error on the mcp3911 has a low temperature coefficient; for more information, see figure 2-34 . 4.8 integral non-linearity error integral non-linearity error is the maximum deviation of an adc transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. it is the maximum remaining error after calibration of offset and gain errors for a dc input signal. 4.9 signal-to-noise ratio (snr) for the mcp3911 adcs, the signal-to-noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal), when the input is a sinewave at a predetermined frequency. it is measured in db. usually, only the maximum signal to noise ratio is specified. the snr figure depends mainly on the osr and dither settings of the device. equation 4-3: signal-to-noise ratio 4.10 signal-to-noise ratio and distortion (sinad) the most important figure of merit for the analog performance of the adcs present on the mcp3911 is the signal-to-noise and distortion (sinad) specification. signal-to-noise and distortion ratio is similar to signal- to-noise ratio, with the exception that you must include the harmonics power in the noise power calculation. the sinad specification depends mainly on the osr and dither settings. equation 4-4: sinad equation the calculated combination of snr and thd per the following formula also yields sinad: equation 4-5: sinad, thd, and snr relationship table 4-3: mcp3911 oversampling ratio settings config over sampling ratio osr osr<2:0> 000 32 001 64 010 128 0 1 1 256 (default) 100 512 1 0 1 1024 1 1 0 2048 1 1 1 4096 snr db () 10 signalpower noisepower ---------------------------------- ?? ?? log = sinad db () 10 signalpower noise harmonicspower + ------------------------------------------------------------------- - ?? ?? log = sinad db () 10 10 snr 10 ----------- ?? ?? 10 thd ? 10 --------------- - ?? ?? + log =
mcp3911 ds22286a-page 26 ? 2012 microchip technology inc. 4.11 total harmonic distortion (thd) the total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sinewave input and is defined by the following equation. equation 4-6: the thd calculation includes the first 35 harmonics for the mcp3911 specifications. the thd is usually only measured with respect to the 10 first harmonics. thd is sometimes expressed in %. for converting the thd in %, here is the formula: equation 4-7: this specification depends mainly on the dither set- ting. 4.12 spurious-free dynamic range (sfdr) the ratio between the output power of the fundamental and the highest spur in the frequency spectrum. the spur frequency is not necessarily a harmonic of the fundamental even though it is usually the case. this figure represents the dynamic range of the adc when a full-scale signal is used at the input. this specification depends mainly on the dither setting. equation 4-8: 4.13 mcp3911 delta-sigma architecture the mcp3911 incorporates two delta-sigma adcs with a multi-bit architecture. a delta-sigma adc is an oversampling converter that incorporates a built-in modulator which is digitizing the quantity of charge integrated by the modulator loop (see figure 5-1 ). the quantizer is the block that is performing the analog-to-digital conversion. the quantizer is typically 1-bit, or a simple comparator which helps to maintain the linearity performance of the adc (the dac structure is, in this case, inherently linear). multi-bit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the osr which leads to better snr figures. however, typically, the linearity of such architectures is more difficult to achieve since the dac is no more simple to realize and its linearity limits the thd of such adcs. the mcp3911?s 5-level quantizer is a flash adc composed of four comparators arranged with equally spaced thresholds and a thermometer coding. the mcp3911 also includes proprietary 5-level dac architecture that is inherently linear for improved thd figures. 4.14 idle tones a delta-sigma converter is an integrating converter. it also has a finite quantization step (lsb) which can be detected by its quantizer. a dc input voltage that is below the quantization step should only provide an all zeros result since the input is not large enough to be detected. as an integrating device, any delta-sigma will show in this case idle tones. this means that the output will have spurs in the frequency content that are depending on the ratio between quantization step voltage and the input voltage. these spurs are the result of the integrated sub-quantization step inputs that will eventually cross the quantization steps after a long enough integration. this will induce an ac frequency at the output of the adc and can be shown in the adc output spectrum. these idle tones are residues that are inherent to the quantization process and the fact that the converter is integrating at all times without being reset. they are residues of the finite resolution of the conversion process. they are very difficult to attenuate and they are heavily signal dependent. they can degrade both sfdr and thd of the converter, even for dc inputs. they can be localized in the baseband of the converter and thus difficult to filter from the actual input signal. for power metering applications, idle tones can be very disturbing because energy can be detected even at the 50 or 60 hz frequency, depending on the dc offset of the adcs, while no power is really present at the inputs. the only practical way to suppress or attenuate idle tones phenomenon is to apply dithering to the adc. the idle tones amplitudes are a function of the order of the modulator, the osr and the number of levels in the quantizer of the modulator. a higher order, a higher osr or a higher number of levels for the quantizer will attenuate the idle tones amplitude. thd db () 10 harmonicspower fundamentalpower ---------------------------------------------------- - ?? ?? log = thd % () 100 10 thd db () 20 ------------------------ = sfdr db () 10 fundamentalpower highestspurpower ---------------------------------------------------- - ?? ?? log =
? 2012 microchip technology inc. ds22286a-page 27 mcp3911 4.15 dithering in order to suppress, or attenuate, the idle tones pres- ent in any delta-sigma adcs, dithering can be applied to the adc. dithering is the process of adding an error to the adc feedback loop in order to ?decorrelate? the outputs and ?break? the idle tones behavior. usually a random or pseudo-random generator adds an analog or digital error to the feedback loop of the delta-sigma adc in order to ensure that no tonal behavior can happen at its outputs. this error is filter by the feedback loop and typically has a zero average value so that the converter static transfer function is not disturbed by the dithering process. however, the dithering process slightly increases the noise floor (it adds noise to the part) while reducing its tonal behavior and thus improving sfdr and thd. (see figure 2-14 and figure 2-18 ). the dithering process scrambles the idle tones into baseband white noise and ensures that dynamic specs (snr, sinad, thd, sfdr) are less signal dependent. the mcp3911 incorporates a proprietary dithering algorithm on both adcs in order to remove idle tones and improve thd, which is crucial for power metering applications. 4.16 crosstalk the crosstalk is defined as the perturbation caused by one adc channel on the other adc channel. it is a measurement of the isolation between the two adcs present in the chip. this measurement is a two-step procedure: 1. measure one adc input with no perturbation on the other adc (adc inputs shorted). 2. measure the same adc input with a perturbation sine wave signal on the other adc at a certain predefined frequency. the crosstalk is then the ratio between the output power of the adc when the perturbation is present and when it is not divided by the power of the perturbation signal. a lower crosstalk value implies more independence and isolation between the two channels. the measurement of this signal is performed under the default conditions at mclk = 4 mhz: ?gain = 1, ? prescale = 1, ? osr = 256, ? mclk = 4 mhz step 1 ? ch0+=ch0-=agnd ? ch1+=ch1-=agnd step 2 ? ch0+=ch0-=agnd ? ch1+ - ch1-=1.2v p-p @ 50/60 hz (full-scale sine wave) the crosstalk is then calculated with the following formula: equation 4-9: 4.17 psrr this is the ratio between a change in the power supply voltage and the adc output codes. it measures the influence of the power supply voltage on the adc outputs. the psrr specification can be dc (the power supply is taking multiple dc values) or ac (the power supply is a sinewave at a certain frequency with a certain common mode). in ac, the amplitude of the sinewave is representing the change in the power supply. it is defined as: equation 4-10: where v out is the equivalent input voltage that the output code translates to with the adc transfer function. in the mcp3911 specification, av dd varies from 2.7v to 3.6v, and for ac psrr a 50/60 hz sinewave is chosen centered around 3.3v with a maximum 300 mv amplitude. the psrr specification is measured with av dd = dv dd . 4.18 cmrr this is the ratio between a change in the common-mode input voltage and the adc output codes. it measures the influence of the common-mode input voltage on the adc outputs. the cmrr specification can be dc (the common-mode input voltage is taking multiple dc values) or ac (the common-mode input voltage is a sinewave at a certain frequency with a certain common mode). in ac, the amplitude of the sinewave is representing the change in the power supply. it is defined as: ctalk db () 10 ch0power ch1power -------------------------------- - ?? ?? log = psrr db () 20 v out av dd ------------------ - ?? ?? log =
mcp3911 ds22286a-page 28 ? 2012 microchip technology inc. equation 4-11: where v cm = (chn+ + chn-)/2 is the common-mode input voltage and v out is the equivalent input voltage that the output code translates to with the adc transfer function. in the mcp3911 specification, vcm varies from -1v to +1v. 4.19 adc reset mode adc reset mode (called also soft reset mode) can only be entered through setting high the reset<1:0> bits in the configuration register. this mode is defined as the condition where the converters are active but their output is forced to 0. the registers are not affected in this reset mode and retain their except the data registers of the correspond- ing channel which are reset to 0. the adcs can immediately output meaningful codes after leaving reset mode (and after the sinc filter settling time). this mode is both entered and exited through setting of bits in the configuration register. each converter can be placed in soft reset mode independently. the configuration registers are not modified by the soft reset mode. a data ready pulse will not be generated by any adc while in reset mode. reset mode also effects the modulator output block, i.e., the mdat pin, corresponding to the channel in reset. if enabled, it provides a bitstream corresponding to a zero output (a series of 0011 bits continuously repeated). when an adc exits adc reset mode, any phase delay present before reset was entered will still be present. if one adc was not in reset, the adc leaving reset mode will resynchronize automatically the phase delay relative to the other adc channel per the phase delay register block and give data ready pulses accordingly. if an adc is placed in reset mode while the other is converting, it is not shutting down the internal clock. when going back out of reset, it will be resynchronized automatically with the clock that did not stop during reset. if both adcs are in soft reset the clock is no longer dis- tributed to the digital core for low power operation. once any of the adc is back to normal operation, the clock is automatically distributed again. however, when the two channels are in soft reset, the input structure is still clocking if mclk is applied in order to bias properly the inputs so that no leakage cur- rent is observed. if mclk is not applied, large analog input leakage currents can be observed for highly neg- ative input voltages (typically below -0.6v referred to agnd). 4.20 hard reset mode (reset = 0) this mode is only available during a por or when the reset pin is pulled low. the reset pin low state places the device in a hard reset mode. in this mode all internal registers are reset to their default state. the dc biases for the analog blocks are still active, i.e., the mcp3911 is ready to convert. however, this pin clears all conversion data in the adcs. in this mode, the mdat outputs are in high impedance. the comparator?s outputs of both adcs are forced to their reset state (0011). the sinc filters are all reset, as well as their double output buffers. see serial timing for minimum pulse low time, in section 1.0 ?electrical characteristics? . during a hard reset, no communication with the part is possible. the digital interface is maintained in a reset state. during this state, the clock mclk can be applied to the part in order to properly bias the input structures of both channels. if not applied, large analog input leakage cur- rents can be observed for highly negative input signals and after removing the reset state a certain start up time is necessary to bias the input structure properly. during this delay the adc conversions can be inaccu- rate. 4.21 adc shutdown mode adc shutdown mode is defined as a state where the converters and their biases are off, consuming only leakage current. when shutdown bit is reset to 0, the analog biases will be enabled, as well as the clock and the digital circuitry. the adc will give a data ready after the sinc filter settling time has occurred. however, since the analog biases are not completely settled at the beginning of the conversion, the sampling may not be accurate during about 1 ms (corresponding to the settling time of the biasing in worst case conditions). in order to guarantee the accuracy, the data ready pulse, coming within the delay of 1 ms + settling time of the sinc filter, should be discarded. each converter can be placed in shutdown mode independently. the config registers are not modified by the shutdown mode. this mode is only available through programming of the shutdown<1:0> bits the config register. the output data is flushed to all zeros while in adc shutdown. no data ready pulses are generated by any adc while in adc shutdown mode. cmrr db () 20 v out v cm ----------------- ?? ?? log =
? 2012 microchip technology inc. ds22286a-page 29 mcp3911 adc shutdown mode also effects the modulator output block, i.e., if mdat of the channel in shutdown mode is enabled, this pin will provide a bitstream corresponding to a zero output (series of 0011 bits continuously repeated). when an adc exits adc shutdown mode, any phase delay present before shutdown was entered will still be present. if one adc was not in shutdown, the adc leaving shutdown mode will automatically resynchronize the phase delay, relative to the other adc channel, per the phase delay register block and give data ready pulses accordingly. if an adc is placed in shutdown mode while the other is converting, it is not shutting down the internal clock. when going back out of shutdown, it will be resynchronized automatically with the clock that did not stop during reset. if both adcs are adc shutdown modes, the clock is no more distributed to the digital core for low power oper- ation. the clock is no more distributed to the input structure too. this can cause potential high analog input leakage currents at the analog inputs if the input voltage is highly negative (typically below -0.6v, referred to agnd). once any of the adc is back to nor- mal operation, the clock is automatically distributed again. 4.22 full shutdown mode the lowest power consumption can be achieved when shutdown<1:0>=11, vrefext=clkext=1. this mode is called ?full shutdown mode?, and no analog circuitry is enabled. in this mode, both av dd and dv dd por monitoring are also disabled. no clock is propa- gated throughout the chip. both adcs are in shutdown, and the internal voltage reference is disabled. the clock is no more distributed to the input structure too. this can cause potential high analog inputs leak- age currents at the analog inputs if the input voltage is highly negative (typically below -0.6v, referred to agnd). the only circuit that remains active is the spi interface but this circuit does not induce any static power consumption. if sck is idle, the only current consumption comes from the leakage currents induced by the transistors and is less than 1 a on each power supply. this mode can be used to power down the chip completely and avoid power consumption when there is no data to convert at the analog inputs. any sck or mclk edge coming while in this mode will induce dynamic power consumption. once any of the shutdown, clkext and vrefext bits return to 0, the two por monitoring blocks are back to operation and av dd and dv dd monitoring can take place. when exiting full shutdown mode, the device resets to its default configuration state. the configuration bits all reset to their default value, and the adcs reset to their initial state, requiring 3 drclk periods for an initial data ready pulse. exiting full shutdown mode is effec- tively identical to an internal reset or returning from a por condition.
mcp3911 ds22286a-page 30 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds22286a-page 31 mcp3911 5.0 device overview 5.1 analog inputs (chn+/-) the mcp3911 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or rogowski coils). each input pin is protected by specialized esd structures that are certified to pass 4.0 kv hbm and 200v mm contact charge. these structures allow bipolar 2v continuous voltage with respect to agnd, to be present at their inputs without the risk of permanent damage. both channels have fully differential voltage inputs for better noise performance. the absolute voltage at each pin, relative to agnd, should be maintained in the 1v range during operation, in order to ensure the specified adc accuracy. the common-mode signals should be adapted to respect both the previous conditions and the differential input voltage range. for best performance, the common-mode signals should be maintained to agnd. 5.2 programmable gain amplifiers (pga) the two programmable gain amplifiers (pgas) reside at the front-end of each delta-sigma adc. they have two functions: translate the common-mode of the input from agnd to an internal level between agnd and a vdd , and amplify the input differential signal. the translation of the common mode does not change the differential signal but recenters the common-mode so that the input signal can be properly amplified. the pga block can be used to amplify very low signals, but the differential input range of the delta-sigma modulator must not be exceeded. the pga is controlled by the pga_chn<2:0> bits in the gain reg- ister. the following table represents the gain settings for the pga: 5.3 delta-sigma modulator 5.3.1 architecture both adcs are identical in the mcp3911, and they include a proprietary second-order modulator with a multi-bit 5-level dac architecture (see figure 5-1 ). the quantizer is a flash adc composed of four compara- tors, with equally spaced thresholds, and a thermome- ter output coding. the proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing linearity or inducing additional distortion. the sampling frequency is dmclk (typically 1 mhz with mclk=4 mhz) so the modulator outputs are refreshed at a dmclk rate. the modulator outputs are available in the mod register or serially transferred on each mdat pin. figure 5-1 represents a simplified block diagram of the delta-sigma adc present on mcp3911. figure 5-1: simplified delta-sigma adc block diagram. 5.3.2 modulator input range and saturation point for a specified voltage reference value of 1.2v, the modulators specified differential input range is 600 mv. the input range is proportional to v ref and scales according to the v ref voltage. this range is guaranteeing the stability of the modulator over amplitude and frequency. outside of this range, the note: if the analog inputs are held to a potential of -0.6 to -1v, for extended periods of time, the clock mclk must be present inside the device in order to avoid large leakage currents at the analog inputs. this is true even during the hard reset mode or the soft reset of both adcs. however during shutdown mode of the two adcs or por state, the clock is not distributed inside the circuit. during these states, it is recom- mended to keep the analog input voltages above -0.6v referred to agnd, to avoid high analog inputs leakage currents. table 5-1: pga configuration setting gain pga_chn<2:0> gain (v/v) gain (db) v in range (v) 000 1 00.6 001 2 60.3 010 4 120.15 0 1 1 8 18 0.075 1 0 0 16 24 0.0375 1 0 1 32 30 0.01875 note: the 2 undefined settings are g=1; this table is defined with v ref = 1.2v. second- order integrator loop filter quantizer dac differential voltage input output bitstream 5-level flash adc mcp3911 delta-sigma modulator
mcp3911 ds22286a-page 32 ? 2012 microchip technology inc. modulator is still functional, however its stability is no longer guaranteed and therefore it is not recommended to exceed this limit (see figure 2-24: ?sinad vs. input signal amplitude.? for extended dynamic range performance limitations). the saturation point for the modulator is v ref /1.5 since the transfer function of the adc includes a gain of 1.5 by default (independent from the pga setting. see section 5.6 ?adc output coding? ). 5.3.3 boost settings the delta-sigma modulators include a programmable biasing circuit in order to further adjust the power con- sumption to the sampling speed applied through the mclk. this can be programmed through the boost<1:0> bits which are applied to both channels simultaneously. the maximum achievable analog master clock speed (amclk) and the maximum sampling frequency (dmclk), and therefore the maximum achievable data rate (drclk), highly depend on boost<1:0> and pga_chn<2:0> settings. the following table specifies the maximum amclk possible to keep optimal accu- racy in function of boost<1:0> and pga_chn<2:0> settings. table 5-2: maximum amclk limits as a function of boost and pga gain conditions v dd = 3.0v to 3.6v, t a from -40c to 125c v dd = 2.7v to 3.6v, t a from -40c to 125c boost gain maximum amclk (mhz) (sinad within -3 db from its maximum) maximum amclk (mhz) (sinad within -5 db from its maximum) maximum amclk (mhz) (sinad within -3 db from its maximum) maximum amclk (mhz) (sinad within - 5 db from its maximum) 0.5x 1 3 3 3 3 0.66x 1 4 4 4 4 1x 1 10 10 10 10 2x 1 16 16 16 16 0.5x 2 2.5 3 3 3 0.66x 2 4 4 4 4 1x 2 10 10 10 10 2x 2 14.5 16 13.3 14.5 0.5x 4 2.5 2.5 2.5 2.5 0.66x 4 4 4 4 4 1x 4 10 10 8 10 2x 4 13.3 16 10.7 11.4 0.5x 8 2.5 2.5 2.5 2.5 0.66x 8 4 4 4 4 1x 8 10 11.4 6.7 8 2x 8 10 14.5 8 8 0.5x 16 2 2 2 2 0.66x 16 4 4 4 4 1x 16 10.6 10.6 8 10 2x 16 12.3 16 8 10.7 0.5x 32 2 2 2 2 0.66x 32 4 4 4 4 1x 32 10 11.4 8 10 2x 32 13.3 16 8 10
? 2012 microchip technology inc. ds22286a-page 33 mcp3911 5.3.4 autozeroing frequency setting (az_freq) the mcp3911 modulators include an autozeroing algo- rithm to improve the offset error performance and greatly diminish 1/f noise in the adc. this algorithm permits it to reach very high snr and flattens the noise spectrum at the output of the adc (see performance graphs figure 2-1 , figure 2-2 , figure 2-3 and figure 2- 4 ). this autozeroing algorithm is performed synchro- nously with the mclk coming to the device, and its rate can be adjusted throughout the az_freq bit in the config register. when az_freq=0 (default) the autozeroing is hap- pening at the slowest rate, which diminishes the 1/f noise while not impacting the thd performance. this mode is recommended for low values of the pga gain (gain=1x or 2x). when az_freq=1, the autozeroing is happening at the fastest rate, which further diminishes the 1/f noise and further improves the snr, especially at higher gain settings. the thd may slightly be impacted in this mode (see figure 2-22 ). this mode is recommended for higher pga gain settings to improve snr (gain superior or equal to 4x). 5.3.5 dither settings both modulators also include a dithering algorithm that can be enabled through the dither<1:0> bits in the configuration register. this dithering process improves thd and sfdr (for high osr settings) while increasing slightly the noise floor of the adcs. for power metering applications and applications that are distortion-sensitive, it is recommended to keep dither at maximum settings for best thd and sfdr performance. in the case of power metering applica- tions, thd and sfdr are critical specifications. opti- mizing snr (noise floor) is not really problematic due to large averaging factor at the output of the adcs, therefore even for low osr settings, the dithering algo- rithm will show a positive impact on the performance of the application. 5.4 modulator output block if the user wishes to use the modulator output of the device, the appropriate bits to enable the modulator output must be set in the configuration register. when modout<1:0> bits are enabled, the modulator output of the corresponding channel is present at the corresponding mdat output pin as soon as the command is placed. additionally, the corresponding sinc filter is disabled in order to consume less current. the corresponding dr pulse is also not present at the dr output pin. when modout<1:0> bits are cleared, the corresponding sinc filters are back to normal oper- ation and the corresponding mdat outputs are in high impedance. since the delta-sigma modulators have a 5-level out- put given by the state of four comparators with ther- mometer coding, their outputs can be represented on four bits, each bit giving the state of the corresponding comparator (see tab l e 5 - 3 ). these bits are present on the mod register and are updated at the dmclk rate. in order to output the comparators result on a separate pin (mdat0 and mdat1), these comparator output bits have been arranged to be serially output at the amclk rate (see figure 5-2 ). this 1-bit serial bitstream is the same that would be produced by a 1-bit dac modulator with a sampling frequency of amclk. the modulator can either be considered like a 5 level-output at dmclk rate, or 1-bit output at amclk rate. these two representations are interchangeable. the mdat outputs can therefore be used in any application that requires 1-bit modulator outputs. these applications will often integrate and filter the 1-bit output with sinc, or more complex decimation filters computed by a mcu or a dsp. table 5-3: delta-sigma modulator coding comp<3:0> code modulator output code mdat serial stream 1111 +2 1111 0111 +1 0111 0011 0 0011 0001 -1 0001 0000 -2 0000
mcp3911 ds22286a-page 34 ? 2012 microchip technology inc. figure 5-2: mdat serial outputs in function of the modulator output code. since the reset and shutdown spi commands are asynchronous, the mdat pins are resynchronized with dmclk after each time the part goes out of reset and shutdown. this means that the first output of mdat, after a soft reset or a shutdown, is always 0011 after the first dmclk rising edge. the two mdat output pins are in high impedance if the reset pin is low. 5.5 sinc 3 + sinc 1 filter the decimation filter present in both channels of the mcp3911 is a cascade of two sinc filters (sinc 3 +sinc 1 ): a third order sinc filter with a decimation ratio of osr 3 followed by first order sinc filter with a decimation ratio of osr 1 (moving average of osr 1 values). figure 5-3 represents the decimation filter architecture. figure 5-3: mcp3911 decimation filter block diagram. the formula for calculating the transfer function of the digital decimation filter and settling time of the adc is as follows: equation 5-1: sinc filter transfer function dmclk mdat+2 mdat+1 mdat+0 mdat-1 mdat-2 comp amclk <3> comp <2> comp <1> comp <0> modulator output sinc 3 sinc 1 decimation filter output osr 3 osr 1 4 16 (width=0) 24 (width=1) decimation filter osr 1 =1 hz () 1 z - osr 3 ? ?? ?? 3 osr 3 1 z 1 ? ? () () 3 --------------------------------------------- 1z - osr 1 osr 3 ? ?? ?? osr 1 1 z - osr 3 ? ?? ?? ---------------------------------------------------------- - where , = z exp 2 jf in ?? dmclk ? () =
? 2012 microchip technology inc. ds22286a-page 35 mcp3911 equation 5-2: setting time of the adc as a function of dmclk periods the sinc 1 filter following the sinc 3 filter is only enabled for the high osr settings. this sinc 1 filter provides additional rejection at a low cost with little modification to the -3 db bandwidth. for 24-bit output mode (width = 1), the output of the sinc filter is pad- ded on the right with least significant zeros, up to 24 bits, for any resolution less than 24 bits. for 16-bit out- put modes, the output of the sinc filter is rounded to the closest 16-bit number, in order to conserve only 16-bit words and to minimize truncation error. the gain of the transfer function of this filter is 1 at each multiple of dmclk (typically 1 mhz) so a proper anti- aliasing filter must be placed at the inputs. this will attenuate the frequency content around dmclk and keep the desired accuracy over the baseband of the converter. this anti-aliasing filter can be a simple, first- order rc network with a sufficiently low time constant to generate high rejection at dmclk frequency . any unsettled data is automatically discarded to avoid data corruption. each data ready pulse corresponds to fully settled data at the output of the decimation filter. the first data available at the output of the decimation filter is present after the complete settling time of the fil- ter (see tab le 5 -4 ). after the first data has been pro- cessed, the delay between two data ready pulses is 1/ drclk. the data stream from input to output is delayed by an amount equal to the settling time of the filter (which is the group delay of the filter). the achievable resolution, the -3 db bandwidth and the settling time at the output of the decimation filter (the output of the adc), is dependent on the osr of each sinc filter and is summarized with the following table: settlingtime dmclkperiods () 3 osr 3 osr 1 1 ? () osr 3 + = table 5-4: oversampling ratio and sinc filter settling time osr<2:0> osr 3 osr 1 total osr resolution in bits (no missing codes) settling time -3 db bandwidth 0 0 0 32 1 32 17 96/dmclk 0.26*drclk 0 0 1 64 1 64 20 192/dmclk 0.26*drclk 0 1 0 128 1 128 23 384/dmclk 0.26*drclk 0 1 1 256 1 256 24 768/dmclk 0.26*drclk 1 0 0 512 1 512 24 1536/dmclk 0.26*drclk 1 0 1 512 2 1024 24 2048/dmclk 0.37*drclk 1 1 0 512 4 2048 24 3072/dmclk 0.42*drclk 1 1 1 512 8 4096 24 5120/dmclk 0.43*drclk
mcp3911 ds22286a-page 36 ? 2012 microchip technology inc. figure 5-4: sinc filter frequency response, osr = 256, mclk = 4 mhz, pre<1:0> = 00. figure 5-5: sinc filter frequency response, osr = 4096 (pink), osr = 512 (blue), mclk = 4 mhz, pre<1:0> = 00.
? 2012 microchip technology inc. ds22286a-page 37 mcp3911 5.6 adc output coding the second order modulator, sinc 3 +sinc 1 filter, pga, v ref and analog input structure, all work together to produce the device transfer function for the analog to digital conversion, equation 5-3 . the channel data is either a 16-bit or 24-bit word, presented in 23-bit or 15-bit plus sign, two?s complement format and is msb (left) justified. the adc data is two or three bytes wide depending on the width bit of the associated channel. the 16-bit mode includes a round to the closest 16-bit word (instead of truncation), in order to improve the accuracy of the adc data. in case of positive saturation (chn+ - chn- > v ref / 1.5), the output is locked to 7fffff for 24 bit mode (7fff for 16 bit mode). in case of negative saturation (chn+ - chn- <-v ref /1.5), the output code is locked to 800000 for 24-bit mode (8000 for 16 bit mode). equation 5-3 is only true for dc inputs. for ac inputs, this transfer function needs to be multiplied by the transfer function of the sinc 3 +sinc 1 filter (see equation 5-1 and equation 5-3 ). equation 5-3: the adc resolution is a function of the osr ( section 5.5 ?sinc3 + sinc1 filter? ). the resolution is the same for both channels. no matter what the res- olution is, the adc output data is always presented in 24-bit words, with added zeros at the end, if the osr is not large enough to produce 24-bit resolution (left justification). data_chn ch n+ ch n- ? () v ref+ v ref- ? ------------------------------------- ?? ?? 8,388,608 g 1.5 = data_chn ch n+ ch n- ? () v ref+ v ref- ? ------------------------------------- ?? ?? 32 768 ,g 1.5 = (for 24-bit mode or width = 1) (for 16-bit mode or width = 0) table 5-5: osr = 256 (and higher) output code examples adc output code (msb first) hexadecimal decimal, 24-bit resolution 0111 1111 1111 1111 1111 1111 0x7fffff + 8,388,607 0111 1111 1111 1111 1111 1110 0x7f fffe + 8,388,606 0000 0000 0000 0000 0000 0000 0x000000 0 1111 1111 1111 1111 1111 1111 0xffffff -1 1000 0000 0000 0000 0000 0001 0x800001 - 8,388,607 1000 0000 0000 0000 0000 0000 0x800000 - 8,388,608 table 5-6: osr = 128 output code examples adc output code (msb first) hexadecimal decimal 23-bit resolution 0111 1111 1111 1111 1111 111 0 0x7ffffe + 4,194,303 0111 1111 1111 1110 1111 110 0 0x7ffffc + 4,194,302 0000 0000 0000 0000 0000 000 0 0x000000 0 1111 1111 1111 1111 1111 111 0 0xfffffe -1 1000 0000 0000 0000 0000 001 0 0x800002 - 4,194,303 1000 0000 0000 0000 0000 000 0 0x800000 - 4,194,304
mcp3911 ds22286a-page 38 ? 2012 microchip technology inc. 5.7 voltage reference 5.7.1 internal voltage reference the mcp3911 contains an internal voltage reference source specially designed to minimize drift over temperature. in order to enable the internal voltage reference, the vrefext bit in the configuration register must be set to 0 (default mode). this internal v ref supplies reference voltage to both channels. the typical value of this voltage reference is 1.2v 2%. the internal reference has a very low typical temperature coefficient of 7 ppm/c, allowing the output to have minimal variation with respect to temperature since they are proportional to (1/v ref ). the noise of the internal voltage reference is low enough not to significantly degrade the snr of the adc if compared to a precision external low-noise voltage reference. the output pin for the internal volt- age reference is refin+/out. if the voltage reference is only used as an internal v ref , adding bypass capacitance on refin+/out is not necessary for keeping adc accuracy, but a minimal 0.1 f ceramic capacitance can be connected to avoid emi/emc susceptibility issues, due to the antenna cre- ated by the refin+/out pin if left floating. the bypass capacitors also help applications where the voltage reference output is connected to other circuits. in this case, additional buffering may be needed as the output drive capability of this output is low. adding too much capacitance on the refin+/out pin may slightly degrade the thd performance of the adcs. 5.7.2 differential external voltage inputs when the vrefext bit is high, the two reference pins (refin+/out, refin-) become a differential voltage reference input. the internal voltage reference circuit is placed into shutdown and the switch connecting this circuit to the reference voltage input of the adc is opened. the internal voltage reference circuit is placed into shutdown and the switch connecting this circuit to the reference voltage input of the adc is opened. the voltage at the refin+/out is noted v ref + and the voltage at the refin- pin is noted v ref -. the differen- tial voltage input value is given by the following equa- tion: equation 5-4: the specified v ref range is from 1.1v to 1.3v. the refin- pin voltage (v ref -) should be limited to 0.1v, with respect to agnd. typically, for single-ended refer- ence applications, the refin- pin should be directly connected to agnd, with its own separate track to avoid any spike due to switching noise. table 5-7: osr = 64 output code examples adc output code (msb first) hexadecimal decimal 20-bit resolution 0111 1111 1111 1111 1111 0 0 0 0 0x7ffff0 + 524, 287 0111 1111 1111 1111 1110 0 0 0 0 0x7fffe0 + 524, 286 0000 0000 0000 0000 0000 0 0 0 0 0x000000 0 1111 1111 1111 1111 1111 0 0 0 0 0xfffff0 -1 1000 0000 0000 0000 0001 0 0 0 0 0x800010 - 524, 287 1000 0000 0000 0000 0000 0 0 0 0 0x800000 - 524, 288 table 5-8: osr = 32 output code examples adc output code (msb first) hexadecimal decimal 17-bit resolution 0111 1111 1111 1111 1 0 0 0 0 0 0 0 0x7fff80 + 65, 535 0111 1111 1111 1111 0 0 0 0 0 0 0 0 0x7fff00 + 65, 534 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0x000000 0 1111 1111 1111 1111 1 0 0 0 0 0 0 0 0xffff80 -1 1000 0000 0000 0000 1 0 0 0 0 0 0 0 0x800080 - 65, 535 1000 0000 0000 0000 0 0 0 0 0 0 0 0 0x800000 - 65, 536 v ref =v ref + - v ref -
? 2012 microchip technology inc. ds22286a-page 39 mcp3911 5.7.3 temperature compensation (vrefcal register) the internal voltage reference comprises a proprietary cir- cuit and algorithm to compensate first order and second order temperature coefficients. the compensation allows very low temperature coefficients (typically 7 ppm/c) on the entire range of temperatures from -40c to 125c. this temperature coefficient varies from part to part. this temperature coefficient can be adjusted on each part through the vrefcal register (address 0x1a). this register is only for advanced users. this register should not be written unless the user wants to calibrate the temperature coefficient of the whole system or application. the default value of this register is set to 0x42. the typical variation of the temperature coeffi- cient of the internal voltage reference, with respect to vrefcal register code, is given by figure 5-6 . modi- fying the value stored in the vrefcal register may also vary the output voltage, in addition to the temperature coefficient. figure 5-6: v ref tempco vs. vrefcal trimcode chart. 5.8 power-on reset the mcp3911 contains an internal por circuit that monitors both analog and digital supply voltages during operation. the typical threshold for a power-up event detection is 2.1 v 5% and a typical start-up time (t por ) of 50 s. the por circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mv. proper decoupling capacitors (0.1 f ceramic and 10 f tantalum) should be mounted as close as possible to the av dd and dv dd pins, providing additional transient immunity. figure 5-7 illustrates the different conditions at power-up and a power-down event in typical conditions. all internal dc biases are not settled until at least 1 ms, in worst case conditions, after system por. any data ready pulse that occurs within 1 ms, plus the sinc filter settling time after system reset, should be ignored to guarantee proper accuracy. after por, data ready pulses are present at the pin with all the default conditions in the configuration registers. both av dd and dv dd are monitored so either power supply can sequence first. figure 5-7: power-on reset operation. 0 10 20 30 40 50 60 0 64 128 192 256 v ref drift (ppm) vrefcal register trim code (decimal) por state power-up normal operation por state biases are unsettled. conversions started here may not be accurate. biases are settled. conversions started here are accurate. analog biases settling time sinc filter settling time any data read pulse occuring during this time can yield inaccurate output data. it is recommended to discard them. voltage (av dd , dv dd ) time por threshold up (2.1v typ.) (1.9v typ.) t por
mcp3911 ds22286a-page 40 ? 2012 microchip technology inc. 5.9 reset effect on delta-sigma modulator/sinc filter when the reset pin is logic low, both adcs will be in reset and output code 0x0000h. the reset pin per- forms a hard reset (dc biases still on, part ready to convert) and clears all charges contained in the delta- sigma modulators. the comparator?s output is 0011 for each adc. the sinc filters are all reset, as well as their double output buffers. this pin is independent of the serial interface. it brings all the registers to the default state. when reset is logic low, any write with the spi interface, will be disabled and will have no effect. all output pins (sdo, dr , mdat0/1) are high impedance. if mclk is applied, the input structure is enabled and is properly biasing the substrate of the input transistors. in this case, the leakage current on the analog inputs is low, if the analog inputs are between -1v and +1v. if mclk is not applied, when in reset mode, the leak- age can be high if the analog inputs are below -0.6v, referred to agnd. 5.10 phase delay block the mcp3911 incorporates a phase delay generator, which ensures that the two adcs are converting the inputs with a fixed delay between them. the two adcs are synchronously sampling but the averaging of modulator outputs is delayed, so that the sinc filter outputs (thus the adc outputs), show a fixed phase delay, as determined by the phase register?s setting. the phase value (phase<11:0>) is a 11 bit + sign, msb first, two's complement code that indicates how much phase delay there is to be between channel 0 and channel 1. the four msb of the first phase register (address 0x07) are undefined and set to 0. the refer- ence channel for the delay is channel 1 (typically the voltage channel for power metering applications). when phase<11:0> is positive, channel 0 is lagging versus channel 1. when phase<11:0> is negative, channel 0 is leading versus channel 1. the amount of delay between two adc conversions is shown in the following formula. equation 5-5: the timing resolution of the phase delay is 1/dmclk, or 1 s in the default configuration with mclk = 4 mhz. the data ready signals are affected by the phase delay settings. typically, the time difference between the data ready pulses of channel 0 and channel 1, is equal to the phase delay setting. 5.10.1 phase delay limits the phase delay can only go from -osr/2 to +osr/2 - 1. this sets the fine phase resolution. the phase register is coded with two's complement. if larger delays between the two channels are needed, they can be implemented externally to the chip with an mcu. a fifo in the mcu can save incoming data from the leading channel for a number n of drclk clocks. in this case, drclk would represent the coarse timing resolution, and dmclk the fine timing resolution. the total delay will then be equal to: delay = n/drclk + phase/dmclk the phase delay register can be programmed once, with the osr=4096 setting, and will adjust to the osr automatically afterwards without the need to change the value of the phase register. ?osr=4096 : the delay can go from -2048 to +2047.phase<11> is the sign bit. phase<10> is the msb and phase<0> the lsb. ?osr=2048 : the delay can go from -1024 to +1023. phase<10> is the sign bit. phase<9> is the msb and phase<0> the lsb. ?osr=1024 : the delay can go from -512 to +511. phase<9> is the sign bit. phase<8> is the msb and phase<0> the lsb. ?osr=512 : the delay can go from -256 to +255. phase<8> is the sign bit. phase<7> is the msb and phase<0> the lsb. ? osr=256 : the delay can go from -128 to +127. phase<7> is the sign bit. phase<6> is the msb and phase<0> the lsb. ? osr=128: the delay can go from -64 to +63. phase<6> is the sign bit. phase<5> is the msb and phase<0> the lsb. ? osr=64 : the delay can go from -32 to +31. phase<5> is the sign bit. phase<4> is the msb and phase<0> the lsb. ? osr=32: the delay can go from -16 to +15. phase<4> is the sign bit. phase<3> is the msb and phase<0> the lsb. delay phase register code dmclk ------------------------------------------------- - = note: a detailed explanation of the data ready pin (dr ) with phase delay is figure 6-9 . note: re-writing the phase registers with the same value resets and automatically restarts both adcs.
? 2012 microchip technology inc. ds22286a-page 41 mcp3911 5.11 crystal oscillator the mcp3911 includes a pierce-type crystal oscillator with very high stability and ensures very low tempco and jitter for the clock generation. this oscillator can handle up to 20 mhz crystal frequencies, provided that proper load capacitances and quartz quality factor are used. for a proper start-up, the load capacitors of the crystal should be connected between osc1 and dgnd and between osc2 and dgnd. they should also respect the following equation: equation 5-6: when clkext=1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock (see figure 4-1 ). when clkext=1, it is recommended to connect osc2 pin to dgnd directly at all times. the external clock should not be higher than 20 mhz before pres- caler (mclk < 20 mhz) for proper operation. 5.12 digital system offset and gain errors the mcp3911 incorporates two sets of additional reg- isters per channel, to perform system digital offset and gain errors calibration. each channel has its own set of registers associated that will modify the output result of the channel, if the calibration is enabled. the gain and offset calibrations can be enabled or disabled through two configuration bits (en_offcal and en_gaincal). these two bits enable or disable sys- tem calibration on both channels at the same time. when both calibrations are enabled, the output of the adc is modified as follows: equation 5-7: digital offset and gain error calibration registers calculations table 5-9: phase values with mclk = 4 mhz, osr = 4096 phase register value hex delay (ch0 relative to ch1) 011111111111 0x7ff + 2047 s 011111111110 0x7fe + 2046 s 000000000001 0x001 + 1 s 000000000000 0x000 0 s 111111111111 0xfff - 1 s 100000000001 0x801 - 2048 s 100000000000 0x800 -2048 s r m 1.6 10 6 1 fc ? load ------------------------ ?? ?? 2 < where: f = crystal frequency in mhz c load = load capacitance in pf including parasitics from the pcb r m = motional resistance in ohms of the quartz note: in addition to the conditions defining the maximum mclk input frequency range, the amclk frequency should be main- tained inferior to the maximum limits defined in ta b l e 5 - 2 to guarantee the accuracy of the adcs. if these limits are exceeded, it is recommended to either choose a larger osr, or a large prescaler value, so that amclk can respect these limits. data_chn post cal ? () data_chn pre cal ? () offcal_chn + () 1 gaincal_chn + () =
mcp3911 ds22286a-page 42 ? 2012 microchip technology inc. 5.12.1 digital offset error calibration the offcal_chn registers are 23-bit plus sign two?s complement register, which lsb value is the same as the channel adc data. these two registers are then added bit-by-bit to the adc output codes, if the en_offcal bit is enabled. enabling the en_offcal bit does not create any pipeline delay, the offset addi- tion is instantaneous. for low osr values, only the sig- nificant digits are added to the output (up to the resolution of the adc. for example, at osr=32, only the 17 first bits are added). the offset is not added when the corresponding chan- nel is in reset or shutdown mode. the corresponding input voltage offset value added by each lsb in these 24-bit registers is: offset(1lsb)= v ref /(pga_chn*1.5*8388608) this register is a don't care if en_offcal=0 (offset calibration disabled), but its value is not cleared by the en_offcal bit. 5.12.2 digital gain error calibration this register is 24-bit signed msb first coding with a range of -1x to +0.9999999x (from 0x80000 to 0x7fffff). the gain calibration adds 1x to this regis- ter and multiplies it to the output code of the channel bit-by-bit, after offset calibration. the range of the gain calibration is thus from 0x to 1.9999999x (from 0x80000 to 0x7fffff). the lsb corresponds to a 2 -23 increment in the multiplier. enabling en_gaincal creates a pipeline delay of 24 dmclk periods on both channels. all data ready pulses are delayed by 24 dmclk periods, starting from the data ready, following the command enabling en_gaincal bit. the gain calibration is effective on the next data ready, following the command enabling en_gaincal bit. the digital gain calibration does not function when the corresponding channel is in reset or shutdown mode. the gain multiplier value for an lsb in these 24-bit reg- isters is: gain (1lsb)= 1/8388608 this register is a don't care if en_gaincal=0 (offset calibration disabled) but its value is not cleared by the en_gaincal bit. the output data on each channel is kept to either 7fff or 8000 (16-bit mode) or 7fffff or 800000 (24-bit mode) if the output result is out of bounds, after all cal- ibrations are performed.
? 2012 microchip technology inc. ds22286a-page 43 mcp3911 6.0 serial interface description 6.1 overview the mcp3911 device is compatible with spi modes 0,0 and 1,1. data is clocked out of the mcp3911 on the falling edge of sck and data is clocked into the mcp3911 on the rising edge of sck. in these modes, sck can idle either high or low. each spi communication starts with a cs falling edge and stops with the cs rising edge. each spi communication is independent. when cs is high, sdo is in high-impedance, transitions on sck, and sdi have no effect. additional controls: reset , dr and mdat0/1 are also provided on separate pins for advanced communication. the mcp3911 interface has a simple command structure. the first byte transmitted is always the control byte and is followed by data bytes that are 8-bits wide. both adcs are continuously converting data by default and can be reset or shut down through a config register setting. since each adc data is either 16 or 24 bits (depending on the width bits), the internal registers can be grouped together with various configurations (through the read bits) in order to allow easy data retrieval within only one communication. for device reads, the internal address counter can be automatically incremented in order to loop through groups of data within the register map. the sdo will then output the data located at the address (a<4:0>) defined in the control byte and then address + 1 depending on the read<1:0> bits, which select the groups of registers. these groups are defined in section 7.1 ?channel registers - adc channel data output registers? (register map). the data ready pin (dr ) can be used as an interrupt for an mcu and outputs pulses when a new adc channel data is available. the reset pin acts like a hard reset and can reset the part to its default power- up configuration. the mdat0/1 pins give the modulator outputs (see section 5.4 ?modulator output block? ). 6.2 control byte the control byte of the mcp3911 contains two device address bits, a<6:5>, 5 register address bits, a<4:0>, and a read/write bit (r/w ). the first byte transmitted to the mcp3911 is always the control byte. the mcp3911 interface is device addressable (through a<6:5>) so that multiple mcp3911 chips can be pres- ent on the same spi bus with no data bus contention. this functionality enables three-phase power metering systems, containing three mcp3911 chips, controlled by a single spi bus (single cs , sck, sdi and sdo pins). figure 6-1: control byte. the default device address bits are ? 00 ?. contact the microchip factory for additional device address bits. for more information, please see the product identification system section. a read on undefined addresses will give an all zeros output on the first, and all subsequent transmitted bytes. a write on an undefined address will have no effect, and also will not increment the address counter. the register map is defined in tab l e 7 - 1 . 6.3 reading from the device the first data byte read is the one defined by the address given in the control byte. after this first byte is transmitted, if the cs pin is maintained low, the communication continues and the address of the next transmitted byte is determined by the status of the read bits in the statuscom register. multiple looping configurations can be defined through the read<1:0> bits for the address increment (see section 6.6 ?spi mode 0,0 ? clock idle low, read/ write examples? ). 6.4 writing to the device the first data byte written is the one defined by the address given in the control byte. two write mode con- figurations for the address increment can be defined through the write bit in the statuscom register. when write = 1 , the write communication automati- cally increments the address for subsequent bytes. the address of the next transmitted byte within the same communication (cs stays logic low) is the next address defined on the register map. at the end of the register map, the address loops to the beginning of the writable part of the register map (address 0x06). writing a non- writable register has no effect. when write = 0 , the address is not incremented on the subsequent writes. the sdo pin stays in high-impedance during a write communication. a6 a5 a4 a3 a2 a1 a0 r/w read/ write bit register device address bits address bits
mcp3911 ds22286a-page 44 ? 2012 microchip technology inc. 6.5 spi mode 1,1 ? clock idle high, read/write examples in this spi mode, sck idles high. for the mcp3911, this means that there will be a falling edge on sck before there is a rising edge. : figure 6-2: device read (spi mode 1,1 ? sck idles high). figure 6-3: device write (spi mode 1,1 ? sck idles high). note: changing from an spi mode 1,1 to an spi mode 0,0 is possible and can be done while cs pin is logic high. sck sdi sdo cs a6 a5 a4 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0 (address) data (address + 1) data d6 d5 d4 d3 d2 d1 data transitions on the falling edge mcu and mcp3911 latch bits on the rising edge d0 hi-z hi-z d7 d7 r/w hi-z sck sdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 (address) data (address + 1) data d6 d5 d4 d3 d2 d1 d0 data transitions on the falling edge mcu and mcp3911 latch bits on the rising edge d0 hi-z hi-z d7 hi-z
? 2012 microchip technology inc. ds22286a-page 45 mcp3911 6.6 spi mode 0,0 ? clock idle low, read/write examples in this spi mode, sck idles low. for the mcp3911, this means that there will be a rising edge on sck before there is a falling edge. figure 6-4: device read (spi mode 0,0 ? sck idles low). figure 6-5: device write (spi mode 0,0 ? sck idles low). sck sdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 (address) data (address + 1) data d7 d6 d5 d4 d3 d2 d1 data transitions on the falling edge mcu and mcp3911 latch bits on the rising edge d0 d7 of (address + 2) data hi-z hi-z hi-z sck sdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d7 (address) data (address + 1) data d6 d5 d4 d3 d2 d1 d7 of (address + 2) data d0 data transitions on the falling edge mcu and mcp3911 latch bits on the rising edge d0 hi-z hi-z hi-z
mcp3911 ds22286a-page 46 ? 2012 microchip technology inc. 6.7 continuous communication, looping on address sets if the user wishes to read back either of the adc channels continuously, or both channels continuously, the internal address counter of the mcp3911 can be set to loop on specific register sets. in this case, there is only one control byte on sdi to start the communication. the part stays within the same loop until cs pin returns logic high. this internal address counter allows the following functionality: ? read one adc channel data continuously ? read both adc channels data continuously (both adc data can be independent or linked with drmode settings) ? continuously read/write the entire register map ? continuously read/write each separate register ? continuously read all configuration registers ? write all configuration registers in one communication (see figure 6-8 ) 6.7.1 continuous read the statuscom register contains the loop settings for the internal address counter (read<1:0> bits and write bit). the internal address counter can either stay constant (read<1:0> = 00 ) and continuously read the same byte, or it can auto-increment and loop through the register groups defined below (read<1:0> = 01 ), register types (read<1:0> = 10 ) or the entire register map (read<1:0> = 11 ). each adc channel is configured independently as either a 16-bit or 24-bit data word, depending on the setting of the corresponding width bit in the statuscom register. for continuous reading, in the case of width = 0 (16-bit), the lower byte of the adc data is not accessed and the part jumps automatically to the following address (the user does not have to clock out the lower byte since it becomes undefined for width = 0 ). figure 6-6 and figure 6-7 represent a typical, continuous read communication with the default settings (drmode<1:0> = 00 , read<1:0> = 10 ) for both width settings in case of the spi mode 0,0 ( figure 6- 6 ) and spi mode 1,1 ( figure 6-7 ). this configuration is typically used for power metering applications. note: for continuous reading of adc data in spi mode 0,0 (see figure 6-6 ), once the data has been completely read after a data ready, the sdo pin will take the msb value of the previous data at the end of the reading (falling edge of the last sck clock). if sck stays idle at logic low (by definition of mode 0,0), the sdo pin will be updated at the falling edge of the next data ready pulse (synchronously with the dr pin falling edge with an output timing of t dodr ) with the new msb of the data corresponding to the data ready pulse. this mechanism allows the mcp3911 to continuously use read mode seamlessly in spi mode 0,0. in spi mode 1,1, the sdo stays in the last state (lsb of previous data) after a complete reading which also allows seamless continuous read mode. (see figure 6-7 ).
? 2012 microchip technology inc. ds22286a-page 47 mcp3911 figure 6-6: typical continuous read communication (spi mode 0,0). figure 6-7: typical continuous read communication (spi mode 1,1). ch0 adc addr/r cs sck sdi ch0 adc upper byte sdo ch0 adc middle byte ch0 adc lower byte dr ch1 adc upper byte ch1 adc middle byte ch1 adc lower byte ch0 adc upper byte new adc data ch0 adc middle byte ch0 adc lower byte ch1 adc upper byte ch1 adc middle byte ch1 adc lower byte these bytes are not present when width=0 (16-bit mode) hiz ch0 adc msb old adc data ch0 adc upper byte old adc data ch0 adc old msb data C previous msb data present on sdo until the data ready pulse updates the sdo with the new incoming msb dta data ch0 adc addr/r cs sck sdi ch0 adc upper byte sdo ch0 adc middle byte ch0 adc lower byte dr ch1 adc upper byte ch1 adc middle byte ch1 adc lower byte ch0 adc upper byte ch0 adc middle byte ch0 adc lower byte ch1 adc upper byte ch1 adc middle byte ch1 adc lower byte these bytes are not present when width=0 (16-bit mode) hiz
mcp3911 ds22286a-page 48 ? 2012 microchip technology inc. 6.7.2 continuous write both adcs are powered up with their default configurations, and begin to output data ready pulses immediately (reset<1:0> and shutdown<1:0> bits are off by default). the default output codes for both adcs are all zeros. the default modulator output for both adcs is ? 0011 ? (corresponding to a theoretical zero voltage at the inputs). the default phase is zero between the two channels. it is recommended to enter into adc reset mode for both adcs, just after power-up, because the desired mcp3911 register configuration may not be the default one, and in this case, the adc would output undesired data. within the adc reset mode (reset<1:0> = 11 ), the user can configure the whole part with a single communication. the write commands automatically increment the address so that the user can start writing the phase register and finish with the config register in only one communication (see figure 6-8 ). the reset<1:0> bits are in the last byte of the config register to allow exiting the soft reset mode, and have the whole part configured and ready to run in only one command. 6.7.3 register groups and types the following register sets are defined as groups: the following register sets are defined as types: 6.8 situations that reset adc data immediately after the following actions, the adcs are reset and automatically restarted in order to provide proper operation: 1. change in phase register 2. change in the osr setting 3. change in the prescale setting 4. overwrite of the same phase register value 5. change in the clkext setting 6. change in the vrefext setting 7. change in the modout setting after these temporary resets, the adcs go back to the normal operation, with no need for an additional command. the phase register can be used to serially soft reset the adcs, without using the reset bits in the configuration register, if the same value is written in the phase register. figure 6-8: recommended configuration sequence at power-up. table 6-1: register groups group addresses adc data ch0 0x00-0x02 adc data ch1 0x03-0x05 mod, phase, gain 0x06-0x09 config, statuscom 0x0a-0x0d offcal_ch0, gaincal_ch0 0x0e-0x13 offcal_ch1, gaincal_ch1 0x14-0x19 vrefcal 0x1a table 6-2: register types type addresses adc data (both channels) 0x00-0x05 configuration 0x06-0x1a 00011010 cs sck sdi av dd , dv dd 11xxxxxx config2 addr/w config2 optional reset of both adcs one command for writing complete configuration (without calibration) phase addr/w gain statuscom config phase 00001110 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
? 2012 microchip technology inc. ds22286a-page 49 mcp3911 6.9 data ready pin (dr ) to signify when channel data is ready for transmission, the data ready signal is available on the data ready pin (dr ) through an active-low pulse at the end of a channel conversion. the data ready pin outputs an active-low pulse with a period that is equal to the drclk clock period, and with a width equal to one dmclk period. when not active-low, this pin can either be in high- impedance (when dr_hiz = 0 ) or in a defined logic high state (when dr_hiz = 1 ). this is controlled through the statuscom register. this allows multiple devices to share the same data ready pin (with a pull-up resistor connected between dr and dv dd ) in 3-phase, energy meter designs to reduce pin count. a single device on the bus does not require a pull-up resistor and therefore it is recommended to use dr_hiz = 1 configuration for such applications. after a data ready pulse has occurred, the adc output data can be read through spi communication. two sets of latches at the output of the adc prevent the communication from outputting corrupted data (see section 6.10 ?adc data latches and data ready modes (drmode<1:0>)? ). the cs pin has no effect on the dr pin, which means even if cs is logic high, data ready pulses will be pro- vided (except when the configuration prevents them from outputting data ready pulses). the dr pin can be used as an interrupt when connected to an mcu or dsp. while the reset pin is logic low, the dr pin is not active. 6.10 adc data latches and data ready modes (drmode<1:0>) to ensure that both channels? adc data is present at the same time for spi read, regardless of phase delay settings for either or both channels, there are two sets of adc data latches in series with both the data ready and the ?read start? triggers. the first set of latches holds each output when the data is ready and latches both outputs together when drmode<1:0> = 00 . when this mode is on, both adcs work together and produce one set of available data after each data ready pulse (that corresponds to the lagging adc data ready). the second set of latches ensures that when reading starts on an adc output, the corresponding data is latched so that no data corruption can occur. if an adc read has started, in order to read the following adc output, the current reading needs to be completed (all bits must be read from the adc output data registers). 6.10.1 data ready pin (dr ) control using drmode bits there are four modes that control the data ready pulses and these modes are set with the drmode<1:0> bits in the statuscom register. for power metering applications, drmode<1:0> = 00 is recommended (default mode). the position of the data ready pulses vary, with respect to this mode, to the osr and to the phase settings: ? drmode<1:0> = 11 : both data ready pulses from adc channel 0 and adc channel 1 are output on the dr pin. ? drmode<1:0> = 10 : data ready pulses from adc channel 1 are output on the dr pin. the data ready pulse from adc channel 0 is not present on the pin. ? drmode<1:0> = 01 : data ready pulses from adc channel 0 are output on the dr pin. the data ready pulse from adc channel 1 is not present on the pin. ? drmode<1:0> = 00 (recommended and default mode): data ready pulses from the lagging adc between the two are output on the dr pin. the lagging adc depends on the phase register and on the osr. in this mode, the two adcs are linked together so their data is latched together when the lagging adc output is ready. 6.10.2 data ready pulses with shutdown or reset conditions there will be no data ready pulses if drmode<1:0> = 00 when either one or both of the adcs are in reset or shutdown. in mode 0,0, a data ready pulse only hap- pens when both adcs are ready. any data ready pulse will correspond to one data on both adcs. the two adcs are linked together and act as if there was only one channel with the combined data of both adcs. this mode is very practical when both adc channels? data retrieval and processing need to be synchronized, as in power metering applications. figure 6-9 represents the behavior of the data ready pin with the different drmode configurations, while shutdown or reset are applied. note: if drmode<1:0> = 11 , the user will still be able to retrieve the data ready pulse for the adc not in shutdown or reset (i.e., only 1 adc channel needs to be awake).
mcp3911 ds22286a-page 50 ? 2012 microchip technology inc. figure 6-9: data ready behavior. d0 d1 d2 d0 d1 d2 d3 d4 d5 d3 d4 d5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d1 d3 d5 d6 d7 d8 d10 d12 d0 d2 d4 d9 d11 d13 d14 d6 d6 d12 d9 d13 d16 d17 d18 d19 d21 d24 d15 d20 d22 d25 d26 d7 d8 d9 d10 d11 d10 d11 d12 d10 d7 d8 d9 d23 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 d12 d13 d14 d15 d16 d0 d1 d2 d4 d5 d3 d7 d8 d9 d10 d11 d12 d13 d6 d15 d16 d14 d0 d1 d2 d6 d10 d11 d12 d13 d11 d13 d14 d15 d16 d12 d13 d14 d14 d28 d29 d31 d33 d27 d30 d32 d34 d15 d16 d17 d8 d7 d9 d4 d5 d3 reset<1> or shutdown<1> reset<0> or shutdown<0> reset d0 d1 d2 d3 d4 d5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d1 d3 d5 d6 d7 d8 d11 d13 d0 d2 d4 d10 d12 d14 d15 d6 d9 d13 d17 d18 d21 d24 d16 d19 d22 d25 d26 d10 d11 d12 d10 d8 d9 d23 d11 d12 d13 d14 d28 d29 d31 d33 d27 d30 d32 d34 d14 d15 d16 d0 d1 d2 d3 d4 d5 d12 d11 d13 d15 d16 d17 d8 d9 d10 d7 phase < 0 phase = 0 phase > 0 d6 d7 drclk period drclk period internal reset synchronisation (1 dmclk period) 3*drclk period 3*drclk period d14 d9 d20 drmode=00; dr drmode=01; dr drmode=10; dr drmode=11; dr drmode=00; dr drmode=01; dr drmode=10; dr drmode=11; dr drmode=00; dr drmode=01; dr drmode=10; dr drmode=11; dr drmode=00: select the lagging data ready drmode=01: select the data ready on channel 0 drmode=10: select the data ready on channel 1 drmode=11: select both data ready drclk period 1 dmclk period internal data ready pulse (filtered be cause it corresponds to unsettled data)
? 2012 microchip technology inc. ds22286a-page 51 mcp3911 7.0 internal registers the addresses associated with the internal registers are listed below. a detailed description of the registers follows. all registers are split in 8-bit long registers, which can be addressed and read separately. read and write modes define the groups and types of regis- ters for continuous read/write communication or loop- ing on address sets as shown in register 7-2 . table 7-1: register map address name bits r/w description 0x00 channel0 24 r channel 0 adc 24-bit data <23:0>, msb first 0x03 channel1 24 r channel 1 adc 24-bit data <23:0>, msb first 0x06 mod 8 r/w modulator output register for both adc channels 0x07 phase 16 r/w phase delay configuration register 0x09 gain 8 r/w gain and boost configuration register 0x0a statuscom 16 r/w status and communication register 0x0c config 16 r/w configuration register 0x0e offcal_ch0 24 r/w offset correction register - channel 0 0x11 gaincal_ch0 24 r/w gain correction register - channel 0 0x14 offcal_ch1 24 r/w offset correction register - channel 1 0x17 gaincal_ch1 24 r/w gain correction register - channel 1 0x1a vrefcal 8 r/w internal voltage reference temperature coefficient adjustment register
mcp3911 ds22286a-page 52 ? 2012 microchip technology inc. . table 7-2: register map grouping fo r all continuous read/write modes function address read<1:0> write = ?11? = ?10? = ?01? = ?00? = ?1? = ?0? channel 0 0x00 loop entire register map type group static loop entire register map static 0x01 static static 0x02 static static channel 1 0x03 group static static 0x04 static static 0x05 static static mod 0x06 type group static static phase 0x07 static static 0x08 static static gain 0x09 static static statuscom 0x0a group static static 0x0b static static config 0x0c static static 0x0d static static offcal_ch0 0x0e group static static 0x0f static static 0x10 static static gaincal_ch0 0x11 static static 0x12 static static 0x13 static static offcal_ch1 0x14 group static static 0x15 static static 0x16 static static gaincal_ch1 0x17 static static 0x18 static static 0x19 static static vrefcal 0x1a group static static
? 2012 microchip technology inc. ds22286a-page 53 mcp3911 7.1 channel registers - adc channel data output registers the adc channel data output registers always con- tain the most recent a/d conversion data for each channel. these registers are read-only. they can be accessed independently or linked together (with read<1:0> bits). these registers are latched when an adc read communication occurs. when a data ready event occurs during a read communication, the most current adc data is also latched to avoid data corrup- tion issues. the three bytes of each channel are updated synchronously at a drclk rate. the three bytes can be accessed separately if needed, but are refreshed synchronously. register 7-1: channel register name bits address r/w channel0 24 0x00 r channel1 24 0x03 r r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data_chn <23> (msb) data_chn <22> data_chn <21> data_chn <20> data_chn <19> data_chn <18> data_chn <17> data_chn <16> bit 23 bit 16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data_chn <15> data_chn <14> data_chn <13> data_chn <12> data_chn <11> data_chn <10> data_chn <9> data_chn <8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 data_chn <7> data_chn <6> data_chn <5> data_chn <4> data_chn <3> data_chn <2> data_chn <1> data_chn <0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23:0 data_chn: output code from adc channel n. this data is post-calibration if the en_offcal or en_gaincal bits are enabled.
mcp3911 ds22286a-page 54 ? 2012 microchip technology inc. 7.2 mod register - modulators output register the mod register contains the most recent modulator data output. the default value corresponds to an equiv- alent input of 0v on both adcs. each bit in this register corresponds to one comparator output on one of the channels. . register 7-2: mod register name bits address cof mod 8 0x06 r/w comparator3 channel 1 comparator2 channel 1 comparator1 channel 1 comparator0 channel 1 comparator3 channel 0 comparator2 channel 0 comparator1 channel 0 comparator0 channel 0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 r/w-1 comp3_ch1 comp2_ch1 comp1_ch1 comp0_ch1 comp3_ch0 comp2_ch0 comp1_ch0 comp0_ch0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7:4 compn_ch1: comparator outputs from adc channel 1 bit 3:0 compn_ch0: comparator outputs from adc channel 0
? 2012 microchip technology inc. ds22286a-page 55 mcp3911 7.3 phase register - phase configuration register any write to one of these two addresses (0x07 and 0x08) creates an internal reset and restart sequence. register 7-3: phase register name bits address cof phase 16 0x07 r/w u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? phase<11> phase<10> phase<9> phase<8> bit 11 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phase<7> phase<6> phase<5> phase<4> phase<3> phase<2> phase<1> phase<0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15:12 unimplemented, read as ? 0 ? bit 11:0 ch0 relative to ch1 phase delay phase<11:0>: ch0 relative to ch1 phase delay bits delay = phase register?s two?s complement code/dmclk (default phase = 0).
mcp3911 ds22286a-page 56 ? 2012 microchip technology inc. 7.4 gain - gain and boost configuration register register 7-4: gain register name bits address cof gain 8 0x09 r/w r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 boost<1> boost<0> pga_ch1<2> pga_ch1<1> pga _ch1<0> pga_ch0<2> pga_ch0<1> pga_ch0<0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7:6 boost<1:0> bias current selection 11 = both channels have current x 2 10 = both channels have current x 1(default) 01 = both channels have current x 0.66 00 = both channels have current x 0.5 bit 5:3 pga_ch1<2:0>: pga setting for channel 1 111 = reserved (gain = 1) 110 = reserved (gain = 1) 101 = gain is 32 100 = gain is 16 011 = gain is 8 010 = gain is 4 001 = gain is 2 000 = gain is 1 (default) bit 2:0 pga_ch0<2:0>: pga setting for channel 0 111 = reserved (gain = 1) 110 = reserved (gain = 1) 101 = gain is 32 100 = gain is 16 011 = gain is 8 010 = gain is 4 001 = gain is 2 000 = gain is 1 (default)
? 2012 microchip technology inc. ds22286a-page 57 mcp3911 7.5 statuscom register - status and communication register register 7-5: statuscom register name bits address cof statuscom 16 0x0a r/w r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 modout<1> modout<0> ? dr_hiz drmode<1> drmode<0> drstatus<1> drstatus<0> bit 15 bit 8 r/w-1 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 u-0 read<1> read<0> write width<1> width<0> en_offcal en_gaincal ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15:14 modout<1:0>: modulator output setting for mdat pins 11 = both ch0 and ch1 modulator outputs are present on mdat1 and mdat0 pins, both sinc fil- ters are off, no data ready pulse is present 10 = ch1 adc modulator output present on mdat1 pin, sinc filter on channel 1 is off, data ready pulse from channel 1 is not present on dr pin 01 = ch0 adc modulator output present on mdat0 pin, sinc filter on channel 0 is off, data ready pulse from channel 0 is not present on dr pin 00 = no modulator output is enabled, sinc filters are on, data readys are present on dr pin for both channels ( default ) bit 13 unimplemented, read as 0 bit 12 dr_hiz : data ready pin inactive state control 1 = the dr pin state is a logic high when data is not ready 0 = the dr pin state is high impedance when data is not ready (default) bit 11:10 drmode<1:0>: data ready pin (dr ) mode configuration bits 11 = both data ready pulses from ch0 and ch1 are output on dr pin 10 = data ready pulses from ch1 adc are output on dr pin. data ready pulses from ch0 are not present on the dr pin. 01 = data ready pulses from ch0 adc are output on dr pin. data ready pulses from ch1 are not present on the dr pin. 00 = data ready pulses from the lagging adc between the two are output on dr pin. the lagging adc depends on the phase register and on the osr. ( default ) bit 9:8 drstatus<1:0>: data ready status 11 = adc channel 1 and channel 0 data not ready ( default ) 10 = adc channel 1 data not ready, adc channel 0 data ready 01 = adc channel 0 data not ready, adc channel 1 data ready 00 = adc channel 1 and channel 0 data ready bit 7:6 read<1:0>: address loop setting 11 = address counter incremented, cycle through entire register set 10 = address counter loops on register types (default) 01 = address counter loops on register groups 00 = address not incremented, continually read single register bit 5 write: address loop setting for write mode 1 = address counter loops on entire register map (default) 0 = address not incremented, continually write same single register
mcp3911 ds22286a-page 58 ? 2012 microchip technology inc. bit 4:3 width<1:0> adc channel output data word width 11 = both channels are in 24-bit mode( default ) 10 = channel1 in 24-bit mode, channel0 in 16-bit mode 01 = channel1 in 16-bit mode, channel0 in 24-bit mode 00 = both channels are in 16-bit mode bit 2 en_offcal enables or disables the 24-bit digital offset calibration on both channels 1 = enabled; this mode does not add any group delay 0 = disabled ( default) bit 1 en_gaincal enables or disables the 24-bit digital offset calibration on both channels 1 = enabled; this mode adds a group delay on both channels of 24 dmclk periods. all data ready pulses are delayed by 24 clock periods compared to the mode with en_gaincal=0 0 = disabled( default ) bit 0 unimplemented, read as 0
? 2012 microchip technology inc. ds22286a-page 59 mcp3911 7.6 config register - configuration register register 7-6: config register name bits address cof config 16 0x0c r/w r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 pre<1> pre<0> osr<2> osr<1> osr<0> dither<1> dither<0> az_freq bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-1 u-0 reset<1> reset<0> shut- down<1> shut- down<0> ? vrefext clkext ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15:14 pre<1:0> analog master clock (amclk) prescaler value 11 = amclk = mclk / 8 10 = amclk = mclk / 4 01 = amclk = mclk / 2 00 = amclk = mclk (default) bit 13:11 osr<2:0> oversampling ratio for delta-sigma a/d conversion (all channels, f d / f s ) 111 = 4096 ( f d = 244 sps for mclk = 4 mhz, f s = amclk = 1 mhz) 110 = 2048 ( f d = 488 sps for mclk = 4 mhz, f s = amclk = 1 mhz) 101 = 1024 ( f d = 976 sps for mclk = 4 mhz, f s = amclk = 1 mhz) 100 = 512 ( f d = 1.953 ksps for mclk = 4 mhz, f s = amclk = 1 mhz) 011 = 256 ( f d = 3.90625 ksps for mclk = 4 mhz, f s = amclk = 1 mhz) (default) 010 = 128 ( f d = 7.8125 ksps for mclk = 4 mhz, f s = amclk = 1 mhz) 001 = 64 ( f d = 15.625 ksps for mclk = 4 mhz, f s = amclk = 1 mhz) 000 = 32 ( f d = 31.25 ksps for mclk = 4 mhz, f s = amclk = 1 mhz) bit 10:9 dither<1:0> control for dithering circuit for idle tones cancellation and improved thd 11 = dithering on, both channels, strength = maximum(mcp3901 equivalent) - (default) 10 = dithering on, both channels, strength = medium 01 = dithering on, both channels, strength = minimum 00 = dithering turned off bit 8 az_freq auto-zero frequency setting 1 = auto-zeroing algorithm running at higher speed 0 = auto-zeroing algorithm running at lower speed (default) bit 7:6 reset<1:0>: reset mode setting for adcs 11 = both ch0 and ch1 adc are in reset mode 10 = ch1 adc in reset mode 01 = ch0 adc in reset mode 00 = neither adc in reset mode(default) bit 5:4 shutdown<1:0>: shutdown mode setting for adcs 11 = both ch0 and ch1 adc in shutdown 10 = ch1 adc in shutdown 01 = ch0 adc in shutdown 00 = neither channel in shutdown(default) bit 3 not implemented, read as 0
mcp3911 ds22286a-page 60 ? 2012 microchip technology inc. 7.7 offcal_chn registers - digital offset error calibration registers bit 2 vrefext internal voltage reference shutdown control 1 = internal voltage reference disabled 0 = internal voltage reference enabled (default) bit 1 clkext internal clock selection bits 1 = external clock drive by mcu on osc1 pin (crystal oscillator disabled, no internal power consumption) (default) 0 = crystal oscillator is enabled. a crystal must be placed between osc1 and osc2 pins. bit 0 not implemented, read as 0 register 7-7: offcal_chn registers name bits address cof offcal_ch0 24 0x0e r/w offcal_ch1 24 0x14 r/w r/w-0 r/w-0 r/w-0 ... r/w-0 r/w-0 r/w-0 r/w-0 offcal_chn <23> offcal_chn <22> offcal_chn <21> ... offcal_chn <3> offcal_chn <2> offcal_chn <1> offcal_chn <0> bit 23 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23:0 digital offset calibration value for the corresponding channel chn. this register simply is added to the output code of the channel bit-by-bit. this register is 24-bit two's complement msb first coding. chn output code = offcal_chn + adc chn output code. this register is a don't care if en_offcal=0 (offset calibration disabled) but its value is not cleared by the en_offcal bit.
? 2012 microchip technology inc. ds22286a-page 61 mcp3911 7.8 gaincal_chn registers - digital gain error calibration registers register 7-8: gaincal_chn registers name bits address cof gaincal_ch0 24 0x11 r/w gaincal_ch1 24 0x17 r/w r/w-0 r/w-0 r/w-0 ... r/w-0 r/w-0 r/w-0 r/w-0 gaincal_chn <23> gaincal_chn <22> gaincal_chn <21> ... gaincal_chn <3> gaincal_chn <2> gaincal_chn <1> gaincal_chn <0> bit 23 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23:0 digital gain error calibration value for the corresponding channel chn. this register is 24-bit signed msb first coding with a range of -1x to +0.9999999x (from 0x80000 to 0x7fffff). the gain calibration adds 1x to this register and multiplies it to the output code of the channel bit by bit, after offset calibra- tion. the range of the gain calibration is thus from 0x to 1.9999999x (from 0x80000 to 0x7fffff). the lsb corresponds to a 2 -23 increment in the multiplier. chn output code = (gaincal_chn+1)*adc chn output code. this register is a don't care if en_gaincal=0 (offset calibration disabled) but its value is not cleared by the en_gaincal bit.
mcp3911 ds22286a-page 62 ? 2012 microchip technology inc. 7.9 vrefcal register ? internal voltage reference temperature coefficient adjustment register this register is only for advanced users. this register should not be written unless the user wants to calibrate the temperature coefficient of the whole system or application. the default value of this register is set to 0x42. register 7-9: vrefcal register name bits address cof vrefcal 8 0x1a r/w r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 vrefcal<7> vrefcal<6> vrefcal<5> vrefcal<4> vrefcal<3> vrefcal<2> vrefcal<1> vrefcal<0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7:0 internal voltage temperature coefficient register value. (see section 5.7.3 ?temperature compensation (vrefcal register)? for complete description).
? 2012 microchip technology inc. ds22286a-page 63 mcp3911 8.0 packaging information 8.1 package marking information 20-lead qfn (4x4x0.9 mm) example : 3 e 3 e 20-lead ssop (ss) example: pin 1 pin 1 e/ml^^ 122256 3911a0 3 e 3911a0 e/ss^^ 1122256 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
mcp3911 ds22286a-page 64 ? 2012 microchip technology inc. d exposed pad e e2 2 1 n top view note 1 n l k b e d2 2 1 a a1 a3 bottom view
? 2012 microchip technology inc. ds22286a-page 65 mcp3911
mcp3911 ds22286a-page 66 ? 2012 microchip technology inc. l l1 a2 c e b a1 a 12 note 1 e1 e d n
? 2012 microchip technology inc. ds22286a-page 67 mcp3911 appendix a: revision history revision a (march 2012) ? original release of this document.
mcp3911 ds22286a-page 68 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds22286a-page 69 mcp3911 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp3911a0: two channel analog font end converter address options: xx a6 a5 a0* = 0 0 a1 = 0 1 a2 = 1 0 a3 = 1 1 * default option. contact microchip factory for other address options tape and reel: t = tape and reel temperature range: e = -40c to +125c package: ml = plastic quad flat no lead package (qfn) ss = small shrink output package (ssop-20) examples: a) mcp3911a0-e/ml: extended temperature, two channel analog front end converter, 20ld qfn package. b) mcp3911a0t-e/ml:tape and reel, extended temperature, two channel analog front end converter, 20ld qfn package. c) mcp3911a0-e/ss: extended temperature, two channel analog front end converter, 20ld ssop package. d) mcp3911a0t-e/ss:tape and reel, extended temperature, two channel analog front end converter, 20ld ssop package. part no. x temperature range device /xx package x tape and reel x x address options
mcp3911 ds22286a-page 70 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds22286a-page 71 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-094-9 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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